Inventor · disambiguated record
David Ian West
Also filed as: WEST DAVID · WEST DAVID IAN
18 granted patents·2 pending applications·54 citations·filing 2007–2017
92Inventor score
Top patents by PatentIndex Score
20 records- 0193US10169262B2Low-power clocking for a high-speed memory interfaceQUALCOMM INC·Filed 2016·Granted Jan 1, 2019·13 cites·30 claims
- 0290US9965352B2Separate link and array error correction in a memory systemQUALCOMM INC·Filed 2016·Granted May 8, 2018·8 cites·23 claims
- 0386US10140175B2Protecting an ECC location when transmitting correction data across a memory linkQUALCOMM INC·Filed 2016·Granted Nov 27, 2018·5 cites·30 claims
- 0481US9881656B2Dynamic random access memory (DRAM) backchannel communication systems and methodsQUALCOMM INC·Filed 2015·Granted Jan 30, 2018·5 cites·18 claims
- 0572US9032358B2Integrated circuit floorplan for compact clock distributionQUALCOMM INC·Filed 2013·Granted May 12, 2015·3 cites·26 claims
- 0670US7882453B2Semiconductor device metal programmable pooling and diesRAPID BRIDGE LLC·Filed 2007·Granted Feb 1, 2011·5 cites·5 claims
- 0770US7642809B2Die apparatus having configurable input/output and control method thereofRAPID BRIDGE LLC·Filed 2007·Granted Jan 5, 2010·6 cites·11 claims
- 0869US9633698B2Dynamic control of signaling power based on an error rateQUALCOMM INC·Filed 2014·Granted Apr 25, 2017·2 cites·30 claims
- 0968US9153560B2Package on package (PoP) integrated device comprising a redistribution layerQUALCOMM INC·Filed 2014·Granted Oct 6, 2015·2 cites·19 claims
- 1066US10061645B2Memory array and link error correction in a low power memory sub-systemQUALCOMM INC·Filed 2015·Granted Aug 28, 2018·1 cites·21 claims
- 1160US9281934B2Clock and data recovery with high jitter tolerance and fast phase lockingQUALCOMM INC·Filed 2014·Granted Mar 8, 2016·1 cites·26 claims
- 1258US9871012B2Method and apparatus for routing die signals using external interconnectsQUALCOMM INC·Filed 2013·Granted Jan 16, 2018·1 cites·31 claims
- 1358US8392865B2Semiconductor device metal programmable pooling and diesMALEKKHOSRAVI BEHNAM·Filed 2011·Granted Mar 5, 2013·1 cites·4 claims
- 1457US9767868B2Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatusesQUALCOMM INC·Filed 2015·Granted Sep 19, 2017·1 cites·19 claims
- 1548US10224081B2Dynamic random access memory (DRAM) backchannel communication systems and methodsQUALCOMM INC·Filed 2017·Granted Mar 5, 2019·0 cites·3 claims
- 1647US9947377B2Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatusesQUALCOMM INC·Filed 2017·Granted Apr 17, 2018·0 cites·19 claims
- 1741US8957714B2Measure-based delay circuitQUALCOMM INC·Filed 2013·Granted Feb 17, 2015·0 cites·13 claims
- 1838US8072240B2Die apparatus having configurable input/output and control method thereofMALEKKHOSRAVI BEHNAM·Filed 2009·Granted Dec 6, 2011·0 cites·9 claims
- 1936US2015213850A1Serial data transmission for dynamic random access memory (dram) interfacesQUALCOMM INC·Filed 2015·Application pending·0 cites
- 2036US2016291634A1Data bandwidth scalable memory systemQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →