Inventor · disambiguated record
Daniel Yen
Also filed as: YEN DANIEL · YEN DANIEL L · YEN DANIEL L W · YEN DANIEL LEE-WEI
23 granted patents·4 pending applications·719 citations·filing 1990–2023
96Inventor score
Files withCHARTERED SEMICONDUCTOR MFG20TAIWAN SEMICONDUCTOR MFG3MACRONIX INT CO LTD2MACRONIX INTERNATIONALCO LTD1MOTIONAL AD LLC1
Top patents by PatentIndex Score
27 records- 0194US5003062ASemiconductor planarization process for submicron devicesTAIWAN SEMICONDUCTOR MFG·Filed 1990·Granted Mar 26, 1991·183 cites·19 claims
- 0293US6632712B1Method of fabricating variable length vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 14, 2003·89 cites·31 claims
- 0390US6576526B2Darc layer for MIM process integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 10, 2003·93 cites·21 claims
- 0490US6468851B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 22, 2002·55 cites·39 claims
- 0585US6630380B1Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM)CHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 7, 2003·44 cites·28 claims
- 0677US7067869B2Adjustable 3D capacitorCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jun 27, 2006·23 cites·15 claims
- 0773US6664153B2Method to fabricate a single gate with dual work-functionsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·18 cites·22 claims
- 0873US6429109B1Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gateCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 6, 2002·18 cites·35 claims
- 0972US6841441B2Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jan 11, 2005·12 cites·37 claims
- 1071US6610575B1Forming dual gate oxide thickness on vertical transistors by ion implantationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·16 cites·47 claims
- 1168US5883001AIntegrated circuit passivation process and structureMACRONIX INT CO LTD·Filed 1994·Granted Mar 16, 1999·51 cites·21 claims
- 1265US12454274B2Methods and apparatuses for transient fault detectionMOTIONAL AD LLC·Filed 2023·Granted Oct 28, 2025·0 cites·19 claims
- 1362US6610604B1Method of forming small transistor gates by using self-aligned reverse spacer as a hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·10 cites·30 claims
- 1457US6689643B2Adjustable 3D capacitorCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 10, 2004·7 cites·13 claims
- 1557US6004622ASpin-on-glass process with controlled environmentMACRONIX INT CO LTD·Filed 1997·Granted Dec 21, 1999·22 cites·18 claims
- 1656US5106787AMethod for high vacuum controlled ramping curing furnace for SOG planarizationTAIWAN SEMICONDUCTOR MFG·Filed 1990·Granted Apr 21, 1992·26 cites·8 claims
- 1755US6713335B2Method of self-aligning a damascene gate structure to isolation regionsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 30, 2004·11 cites·33 claims
- 1854US6544848B1Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacersCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 8, 2003·6 cites·25 claims
- 1948US6803305B2Method for forming a via in a damascene processCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 12, 2004·4 cites·21 claims
- 2047US6828082B2Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 7, 2004·1 cites·51 claims
- 2146US6686279B2Method for reducing gouging during via formationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 3, 2004·4 cites·14 claims
- 2243US5716673ASpin-on-glass process with controlled environmentMACRONIX INTERNATIONALCO LTD·Filed 1994·Granted Feb 10, 1998·17 cites·21 claims
- 2343US2005089777A1Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 2443US2005101083A1Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 2538US5174043AMachine and method for high vacuum controlled ramping curing furnace for sog planarizationTAIWAN SEMICONDUCTOR MFG·Filed 1992·Granted Dec 29, 1992·9 cites·12 claims
- 2638US2004266155A1Formation of small gates beyond lithographic limitsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 2736US2004077174A1Method for forming a high aspect ratio viaCHARTERED SEMICONDUCTOR MFG·Filed 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →