Inventor · disambiguated record
Debra Bernstein
Also filed as: BERNSTEIN DEBRA
79 granted patents·12 pending applications·3,034 citations·filing 1988–2021
99Inventor score
Files withINTEL CORP80DIGITAL EQUIPMENT CORP4JAIN SANJEEV2INTEL CORP A CALIFORNIA CORP1WOLRICH GILBERT1
Top patents by PatentIndex Score
91 records- 0196US6868476B2Software controlled content addressable memory in a general purpose execution datapathINTEL CORP·Filed 2002·Granted Mar 15, 2005·105 cites·22 claims
- 0296US6694380B1Mapping requests from a processing unit that uses memory-mapped input-output spaceINTEL CORP·Filed 1999·Granted Feb 17, 2004·227 cites·27 claims
- 0396US6667920B2Scratchpad memoryINTEL CORP·Filed 2003·Granted Dec 23, 2003·76 cites·15 claims
- 0495US6587906B2Parallel multi-threaded processingINTEL CORP·Filed 2003·Granted Jul 1, 2003·84 cites·17 claims
- 0595US6577542B2Scratchpad memoryINTEL CORP·Filed 2001·Granted Jun 10, 2003·74 cites·19 claims
- 0694US6681300B2Read lock miss control and queue managementINTEL CORP·Filed 2001·Granted Jan 20, 2004·89 cites·18 claims
- 0794US6307789B1Scratchpad memoryINTEL CORP·Filed 1999·Granted Oct 23, 2001·79 cites·22 claims
- 0893US6631462B1Memory shared between processing threadsINTEL CORP·Filed 2000·Granted Oct 7, 2003·74 cites·29 claims
- 0993US6625654B1Thread signaling in multi-threaded network processorINTEL CORP·Filed 1999·Granted Sep 23, 2003·164 cites·16 claims
- 1092US7216204B2Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environmentINTEL CORP·Filed 2002·Granted May 8, 2007·76 cites·20 claims
- 1192US6668317B1Microengine for parallel processor architectureINTEL CORP·Filed 1999·Granted Dec 23, 2003·157 cites·41 claims
- 1292US6532509B1Arbitrating command requests in a parallel multi-threaded processing systemINTEL CORP·Filed 1999·Granted Mar 11, 2003·150 cites·35 claims
- 1391US7366865B2Enqueueing entries in a packet queue referencing packetsINTEL CORP·Filed 2004·Granted Apr 29, 2008·67 cites·42 claims
- 1490US10445271B2Multi-core communication acceleration using hardware queue deviceINTEL CORP·Filed 2016·Granted Oct 15, 2019·7 cites·19 claims
- 1590US7546444B1Register set used in multithreaded parallel processor architectureINTEL CORP·Filed 2000·Granted Jun 9, 2009·59 cites·20 claims
- 1690US7246197B2Software controlled content addressable memory in a general purpose execution datapathINTEL CORP·Filed 2005·Granted Jul 17, 2007·20 cites·18 claims
- 1790US6934951B2Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical sectionINTEL CORP·Filed 2002·Granted Aug 23, 2005·54 cites·25 claims
- 1890US6876561B2Scratchpad memoryINTEL CORP·Filed 2003·Granted Apr 5, 2005·35 cites·13 claims
- 1989US7111296B2Thread signaling in multi-threaded processorINTEL CORP·Filed 2003·Granted Sep 19, 2006·45 cites·27 claims
- 2088US7020871B2Breakpoint method for parallel hardware threads in multithreaded processorINTEL CORP·Filed 2000·Granted Mar 28, 2006·62 cites·12 claims
- 2187US6661794B1Method and apparatus for gigabit packet assignment for multithreaded packet processingINTEL CORP·Filed 1999·Granted Dec 9, 2003·135 cites·27 claims
- 2286US7191321B2Microengine for parallel processor architectureINTEL CORP·Filed 2003·Granted Mar 13, 2007·38 cites·22 claims
- 2386US6792488B2Communication between processorsINTEL CORP·Filed 2003·Granted Sep 14, 2004·33 cites·30 claims
- 2485US10216668B2Technologies for a distributed hardware queue managerINTEL CORP·Filed 2016·Granted Feb 26, 2019·5 cites·29 claims
- 2585US7302549B2Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data accessINTEL CORP·Filed 2005·Granted Nov 27, 2007·13 cites·18 claims
- 2685US6779084B2Enqueue operations for multi-buffer packetsINTEL CORP·Filed 2002·Granted Aug 17, 2004·45 cites·30 claims
- 2784US6895457B2Bus interface with a first-in-first-out memoryINTEL CORP·Filed 2003·Granted May 17, 2005·32 cites·20 claims
- 2884US6560667B1Handling contiguous memory references in a multi-queue systemINTEL CORP·Filed 1999·Granted May 6, 2003·108 cites·23 claims
- 2983US6738831B2Command orderingINTEL CORP·Filed 2001·Granted May 18, 2004·35 cites·30 claims
- 3083US6584522B1Communication between processorsINTEL CORP·Filed 1999·Granted Jun 24, 2003·78 cites·38 claims
- 3183US6324624B1Read lock miss control and queue managementINTEL CORP·Filed 1999·Granted Nov 27, 2001·88 cites·24 claims
- 3282US7328289B2Communication between processorsINTEL CORP·Filed 2004·Granted Feb 5, 2008·23 cites·17 claims
- 3382US6631430B1Optimizations to receive packet status from fifo busINTEL CORP·Filed 1999·Granted Oct 7, 2003·58 cites·30 claims
- 3480US7158964B2Queue managementINTEL CORP·Filed 2001·Granted Jan 2, 2007·28 cites·31 claims
- 3579US7991983B2Register set used in multithreaded parallel processor architectureINTEL CORP·Filed 2009·Granted Aug 2, 2011·7 cites·22 claims
- 3678US12405843B2Infrastructure processing unitINTEL CORP·Filed 2020·Granted Sep 2, 2025·1 cites·22 claims
- 3778US8380923B2Queue arrays in network devicesINTEL CORP·Filed 2010·Granted Feb 19, 2013·4 cites·11 claims
- 3878US7487505B2Multithreaded microprocessor with register allocation based on number of active threadsINTEL CORP·Filed 2002·Granted Feb 3, 2009·21 cites·21 claims
- 3978US7269179B2Control mechanisms for enqueue and dequeue operations in a pipelined network processorINTEL CORP·Filed 2001·Granted Sep 11, 2007·26 cites·14 claims
- 4077US7751402B2Method and apparatus for gigabit packet assignment for multithreaded packet processingINTEL CORP·Filed 2003·Granted Jul 6, 2010·18 cites·20 claims
- 4177US7181594B2Context pipelinesINTEL CORP·Filed 2002·Granted Feb 20, 2007·24 cites·38 claims
- 4276US6463072B1Method and apparatus for sharing access to a busINTEL CORP·Filed 1999·Granted Oct 8, 2002·90 cites·17 claims
- 4375US7225281B2Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanismsINTEL CORP·Filed 2002·Granted May 29, 2007·19 cites·26 claims
- 4475US5542058APipelined computer with operand context queue to simplify context-dependent execution flowDIGITAL EQUIPMENT CORP·Filed 1994·Granted Jul 30, 1996·66 cites·20 claims
- 4574US10929323B2Multi-core communication acceleration using hardware queue deviceINTEL CORP·Filed 2019·Granted Feb 23, 2021·1 cites·25 claims
- 4674US7181573B2Queue array caching in network devicesINTEL CORP·Filed 2002·Granted Feb 20, 2007·19 cites·30 claims
- 4773US7337275B2Free list and ring data structure managementINTEL CORP·Filed 2002·Granted Feb 26, 2008·18 cites·76 claims
- 4873US7149226B2Processing data packetsINTEL CORP·Filed 2002·Granted Dec 12, 2006·18 cites·22 claims
- 4972US7107413B2Write queue descriptor count instruction for high speed queuingINTEL CORP·Filed 2001·Granted Sep 12, 2006·15 cites·13 claims
- 5071US9128818B2Memory mapping in a processor having multiple programmable unitsINTEL CORP·Filed 2014·Granted Sep 8, 2015·1 cites·16 claims
Showing the top 50 of 91 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →