Inventor · disambiguated record
Denis Foley
Also filed as: FOLEY DENIS · FOLEY DENIS J
28 granted patents·5 pending applications·591 citations·filing 1994–2024
97Inventor score
Files withDIGITAL EQUIPMENT CORP10NVIDIA CORP4ATI TECHNOLOGIES ULC3ADVANCED MICRO DEVICES INC2COMPAQ COMPUTER CORP2
Top patents by PatentIndex Score
33 records- 0194US5566325AMethod and apparatus for adaptive memory accessDIGITAL EQUIPMENT CORP·Filed 1994·Granted Oct 15, 1996·164 cites·6 claims
- 0290US8051312B2Apparatus and method for reducing power consumption by an integrated circuitADVANCED MICRO DEVICES INC·Filed 2008·Granted Nov 1, 2011·22 cites·27 claims
- 0389US11182309B2Techniques for an efficient fabric attached memoryNVIDIA CORP·Filed 2019·Granted Nov 23, 2021·7 cites·16 claims
- 0484US11822491B2Techniques for an efficient fabric attached memoryNVIDIA CORP·Filed 2021·Granted Nov 21, 2023·1 cites·16 claims
- 0583US11931522B2Inflation lumen kink protection and balloon profileNEURAVI LTD·Filed 2019·Granted Mar 19, 2024·3 cites·24 claims
- 0682US12434035B2Inflation lumen kink protection and balloon profileNEURAVI LTD·Filed 2024·Granted Oct 7, 2025·0 cites·9 claims
- 0782US8291249B2Method and apparatus for transitioning devices between power states based on activity request frequencyBRANOVER ALEXANDER·Filed 2009·Granted Oct 16, 2012·11 cites·24 claims
- 0873US5761731AMethod and apparatus for performing atomic transactions in a shared memory multi processor systemDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jun 2, 1998·64 cites·14 claims
- 0972US5537575ASystem for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status informationFiled 1994·Granted Jul 16, 1996·61 cites·4 claims
- 1067US8397079B2Method and apparatus for securing digital information on an integrated circuit read only memory during test operating modesGADELRAB SERAG M·Filed 2008·Granted Mar 12, 2013·3 cites·11 claims
- 1167US8051345B2Method and apparatus for securing digital information on an integrated circuit during test operating modesATI TECHNOLOGIES ULC·Filed 2008·Granted Nov 1, 2011·6 cites·11 claims
- 1266US7345239B2System and method for routing cablesHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 18, 2008·19 cites·35 claims
- 1361US5625805AClock architecture for synchronous system bus which regulates and adjusts clock skewDIGITAL EQUIPMENT CORP·Filed 1994·Granted Apr 29, 1997·36 cites·7 claims
- 1460US8156317B2Integrated circuit with secure boot from a debug access port and method thereforESLIGER JAMES LYALL·Filed 2008·Granted Apr 10, 2012·3 cites·20 claims
- 1560US5848258AMemory bank addressing schemeDIGITAL EQUIPMENT CORP·Filed 1996·Granted Dec 8, 1998·40 cites·12 claims
- 1656US6076129ADistributed data bus sequencing for a system bus with separate address and data bus protocolsDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jun 13, 2000·27 cites·5 claims
- 1755US6360285B1Apparatus for determining memory bank availability in a computer systemCOMPAQ COMPUTER CORP·Filed 1994·Granted Mar 19, 2002·28 cites·38 claims
- 1855US5666551ADistributed data bus sequencing for a system bus with separate address and data bus protocolsDIGITAL EQUIPMENT CORP·Filed 1996·Granted Sep 9, 1997·25 cites·27 claims
- 1953US5559987AMethod and apparatus for updating a duplicate tag status in a snoop bus protocol based computer systemDIGITAL EQUIPMENT CORP·Filed 1994·Granted Sep 24, 1996·25 cites·6 claims
- 2050US9720768B2System and method for early packet header verificationNVIDIA CORP·Filed 2015·Granted Aug 1, 2017·0 cites·17 claims
- 2149US2009170550A1Method and Apparatus for Portable Phone Based Noise CancellationFOLEY DENIS J·Filed 2007·Application pending·0 cites
- 2248US10200154B2System and method for early packet header verificationNVIDIA CORP·Filed 2017·Granted Feb 5, 2019·0 cites·20 claims
- 2347US2009287895A1Secure Memory Access SystemADVANCED MICRO DEVICES INC·Filed 2008·Application pending·0 cites
- 2447US2010017893A1System for Securing Register Space and Method of Securing the SameATI TECHNOLOGIES ULC·Filed 2008·Application pending·0 cites
- 2547US2009285390A1Integrated circuit with secured software image and method thereforATI TECHNOLOGIES ULC·Filed 2008·Application pending·0 cites
- 2646US9043625B2Processor bridge power managementSTEINMAN MAURICE B·Filed 2012·Granted May 26, 2015·0 cites·20 claims
- 2746US8205064B2Latency hiding for a memory management unit page table lookupVIVENZIO ANTHONY F·Filed 2007·Granted Jun 19, 2012·2 cites·20 claims
- 2844US5758106AArbitration unit which requests control of the system bus prior to determining whether such control is requiredDIGITAL EQUIPMENT CORP·Filed 1996·Granted May 26, 1998·17 cites·30 claims
- 2943US2007226456A1System and method for employing multiple processors in a computer systemSHAW MARK·Filed 2006·Application pending·0 cites
- 3037US5737546ASystem bus with separate address and data bus protocolsDIGITAL EQUIPMENT CORP·Filed 1996·Granted Apr 7, 1998·10 cites·12 claims
- 3135US6418176B1Forwarded clock recovery with variable latencyCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Jul 9, 2002·7 cites·20 claims
- 3235US5638538ATurbotable: apparatus for directing address and commands between multiple consumers on a node coupled to a pipelined system busDIGITAL EQUIPMENT CORP·Filed 1995·Granted Jun 10, 1997·8 cites·14 claims
- 3331US6256694B1Distributed early arbitrationCOMPAQ COMPUTER CORP·Filed 1994·Granted Jul 3, 2001·2 cites·13 claims
Join the waitlist — get patent alerts
Get an alert when Denis Foley files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →