Inventor · disambiguated record
Debabrata Mohapatra
Also filed as: MOHAPATRA DEBABRATA
12 granted patents·11 pending applications·5 citations·filing 2016–2025
83Inventor score
Files withINTEL CORP23
Top patents by PatentIndex Score
23 records- 0190US12141683B2Performance scaling for dataflow deep neural network hardware acceleratorsINTEL CORP·Filed 2021·Granted Nov 12, 2024·3 cites·20 claims
- 0285US2025365009A1Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectorsINTEL CORP·Filed 2025·Application pending·0 cites
- 0382US12147836B2Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning acceleratorsINTEL CORP·Filed 2021·Granted Nov 19, 2024·1 cites·31 claims
- 0481US11922178B2Methods and apparatus to load data within a machine learning acceleratorINTEL CORP·Filed 2021·Granted Mar 5, 2024·1 cites·20 claims
- 0578US12438553B2Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectorsINTEL CORP·Filed 2023·Granted Oct 7, 2025·0 cites·20 claims
- 0676US2025322218A1System and method for balancing sparsity in weights for accelerating deep neural networksINTEL CORP·Filed 2025·Application pending·0 cites
- 0775US12288153B2Schedule-aware tensor distribution moduleINTEL CORP·Filed 2024·Granted Apr 29, 2025·0 cites·20 claims
- 0875US12242861B2Methods and apparatus to load data within a machine learning acceleratorINTEL CORP·Filed 2024·Granted Mar 4, 2025·0 cites·17 claims
- 0974US2025036928A1Performance scaling for dataflow deep neural network hardware acceleratorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1073US2025028565A1Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning acceleratorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1165US12367380B2System and method for balancing sparsity in weights for accelerating deep neural networksINTEL CORP·Filed 2021·Granted Jul 22, 2025·0 cites·25 claims
- 1265US11804851B2Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectorsINTEL CORP·Filed 2020·Granted Oct 31, 2023·0 cites·21 claims
- 1362US12229673B2Sparsity-aware datastore for inference processing in deep neural network architecturesINTEL CORP·Filed 2021·Granted Feb 18, 2025·0 cites·25 claims
- 1456US11907827B2Schedule-aware tensor distribution moduleINTEL CORP·Filed 2019·Granted Feb 20, 2024·0 cites·18 claims
- 1554US2022188075A1Floating point multiply-accumulate unit for deep learningINTEL CORP·Filed 2022·Application pending·0 cites
- 1653US2022188638A1Data reuse in deep learningINTEL CORP·Filed 2022·Application pending·0 cites
- 1753US2022261623A1System and method for channel-separable operations in deep neural networksINTEL CORP·Filed 2022·Application pending·0 cites
- 1852US12386618B2Multi-buffered register files with shared access circuitsINTEL CORP·Filed 2020·Granted Aug 12, 2025·0 cites·22 claims
- 1952US2022075659A1Runtime configurable register files for artificial intelligence workloadsINTEL CORP·Filed 2021·Application pending·0 cites
- 2047US2022292366A1Methods and apparatus to perform low overhead sparsity acceleration logic for multi-precision dataflow in deep neural network acceleratorsINTEL CORP·Filed 2022·Application pending·0 cites
- 2146US2021042617A1Accelerated loading of unstructured sparse data in machine learning architecturesINTEL CORP·Filed 2020·Application pending·0 cites
- 2245US2021397414A1Area and energy efficient multi-precision multiply-accumulate unit-based processorINTEL CORP·Filed 2021·Application pending·0 cites
- 2340US11010166B2Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuitsINTEL CORP·Filed 2016·Granted May 18, 2021·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →