Inventor · disambiguated record
Debaleena Nandi
Also filed as: NANDI DEBALEENA
2 granted patents·8 pending applications·0 citations·filing 2021–2024
24Inventor score
Files withINTEL CORP10
Top patents by PatentIndex Score
10 records- 0157US12426342B2Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stabilityINTEL CORP·Filed 2021·Granted Sep 23, 2025·0 cites·8 claims
- 0256US12439669B2Co-deposition of titanium and silicon for improved silicon germanium source and drain contactsINTEL CORP·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 0353US2025393251A1Integrated circuit structure with backside conductive feed-throughINTEL CORP·Filed 2024·Application pending·0 cites
- 0452US2025220950A1Transistors with asymmetric source and drain contactsINTEL CORP·Filed 2023·Application pending·0 cites
- 0552US2025006806A1High conductivity transistor contacts comprising gallium enriched layerINTEL CORP·Filed 2023·Application pending·0 cites
- 0652US2025220978A1Integrated circuit structure with asymmetric epitaxial source or drain arrangementsINTEL CORP·Filed 2023·Application pending·0 cites
- 0749US2023193473A1Titanium contact formationINTEL CORP·Filed 2021·Application pending·0 cites
- 0848US2024355915A1Backside conductive structures extending through integrated circuit to meet frontside contactsINTEL CORP·Filed 2023·Application pending·0 cites
- 0948US2024332302A1Integrated circuit structures with backside conductive source or drain contact having enhanced contact areaINTEL CORP·Filed 2023·Application pending·0 cites
- 1046US2023101725A1Silicon rich capping layer pre-amorphized with germanium and boron implants for thermal stability and low pmos contact resistivityINTEL CORP·Filed 2021·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Debaleena Nandi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →