Inventor · disambiguated record
Deviprasad Natesan
Also filed as: NATESAN DEVIPRASAD
9 granted patents·216 citations·filing 2009–2018
89Inventor score
Top patents by PatentIndex Score
9 records- 0197US9998247B1Controller-based network device timing synchronizationJUNIPER NETWORKS INC·Filed 2014·Granted Jun 12, 2018·123 cites·33 claims
- 0293US8954609B1Time adjustment using time-to-live valuesHOLLEMAN KEITH E·Filed 2012·Granted Feb 10, 2015·51 cites·34 claims
- 0392US10284318B1Controller-based network device timing synchronizationJUNIPER NETWORKS INC·Filed 2018·Granted May 7, 2019·10 cites·18 claims
- 0489US8494011B2Apparatus and method of compensating for clock frequency and phase variations by processing packet delay valuesBARRY CHARLES F·Filed 2012·Granted Jul 23, 2013·9 cites·9 claims
- 0589US8031747B2Apparatus and method of compensating for clock frequency and phase variations by processing packet delay valuesJUNIPER NETWORKS INC·Filed 2009·Granted Oct 4, 2011·12 cites·30 claims
- 0680US8270438B2Apparatus and method of compensating for clock frequency and phase variations by processing packet delay valuesBARRY CHARLES F·Filed 2011·Granted Sep 18, 2012·4 cites·20 claims
- 0772US8670459B2Apparatus and method of scheduling timing packets to enhance time distribution in telecommunication networksBARRY CHARLES FREDERICK·Filed 2009·Granted Mar 11, 2014·6 cites·25 claims
- 0866US9319164B2Apparatus and method of compensating for clock frequency and phase variations by processing packet delay valuesJUNIPER NETWORKS INC·Filed 2013·Granted Apr 19, 2016·1 cites·19 claims
- 0952US9621290B2Apparatus and method of compensating for clock frequency and phase variations by processing packet delay valuesJUNIPER NETWORKS INC·Filed 2016·Granted Apr 11, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →