Inventor · disambiguated record
Dheemanth Nagaraj
Also filed as: NAGARAJ DHEEMANTH
11 granted patents·1 pending application·48 citations·filing 2007–2021
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
12 records- 0187US8473791B2Redundant memory to mask DRAM failuresSHAW MARK·Filed 2007·Granted Jun 25, 2013·19 cites·9 claims
- 0282US8656115B2Extending a cache coherency snoop broadcast protocol with directory informationKOTTAPALLI SAILESH·Filed 2010·Granted Feb 18, 2014·6 cites·20 claims
- 0382US7996710B2Defect management for a semiconductor memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Aug 9, 2011·13 cites·22 claims
- 0472US8862918B2Efficient frequency boost operationGANESAN BASKARAN·Filed 2011·Granted Oct 14, 2014·4 cites·27 claims
- 0561US8799586B2Memory mirroring and migration at home agentKUMAR GANESH·Filed 2009·Granted Aug 5, 2014·3 cites·23 claims
- 0658US9298629B2Extending a cache coherency snoop broadcast protocol with directory informationINTEL CORP·Filed 2014·Granted Mar 29, 2016·0 cites·20 claims
- 0758US8327228B2Home agent data and memory managementKUMAR GANESH·Filed 2009·Granted Dec 4, 2012·2 cites·35 claims
- 0856US8918592B2Extending a cache coherency snoop broadcast protocol with directory informationINTEL CORP·Filed 2013·Granted Dec 23, 2014·0 cites·16 claims
- 0955US9235520B2Protocol for conflicting memory transactionsARORA MANOJ K·Filed 2011·Granted Jan 12, 2016·1 cites·20 claims
- 1050US12294368B2Three-dimensional stacked programmable logic fabric and processor design architectureINTEL CORP·Filed 2021·Granted May 6, 2025·0 cites·20 claims
- 1146US8782347B2Controllably exiting an unknown state of a cache coherency directoryKUMAR GANESH·Filed 2009·Granted Jul 15, 2014·0 cites·12 claims
- 1242US2022044123A1Embedded Programmable Logic Device for Acceleration in Deep Learning-Focused ProcessorsVIVEKANANDHAM RAJESH·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →