Inventor · disambiguated record
Dharmesh Parikh
Also filed as: PARIKH DHARMESH
10 granted patents·62 citations·filing 2001–2023
86Inventor score
Top patents by PatentIndex Score
10 records- 0187US8612295B2Method and apparatus for processing order related messagesGIDWANI ARVIND D·Filed 2011·Granted Dec 17, 2013·15 cites·20 claims
- 0284US8019647B1Methods, apparatus and computer readable medium for processing order related messagesCISCO TECH INC·Filed 2007·Granted Sep 13, 2011·13 cites·21 claims
- 0383US7203658B1Methods and apparatus for processing order related messagesCISCO TECH INC·Filed 2001·Granted Apr 10, 2007·30 cites·9 claims
- 0473US9703711B2Managing cache coherence for memory cachesIBM·Filed 2015·Granted Jul 11, 2017·2 cites·11 claims
- 0572US11042312B2DRAM bank activation managementIBM·Filed 2019·Granted Jun 22, 2021·1 cites·20 claims
- 0662US12298903B2Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refreshQUALCOMM INC·Filed 2023·Granted May 13, 2025·0 cites·28 claims
- 0760US10572168B2DRAM bank activation managementIBM·Filed 2017·Granted Feb 25, 2020·1 cites·20 claims
- 0855US11749332B2Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refreshQUALCOMM INC·Filed 2021·Granted Sep 5, 2023·0 cites·40 claims
- 0949US10380040B2Memory request scheduling to improve bank group utilizationIBM·Filed 2017·Granted Aug 13, 2019·0 cites·17 claims
- 1048US9703710B2Managing cache coherence for memory cachesIBM·Filed 2015·Granted Jul 11, 2017·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →