Inventor · disambiguated record
Dimitri Argyres
Also filed as: ARGYRES DIMITRI · ARGYRES DIMITRI C
24 granted patents·760 citations·filing 1995–2013
96Inventor score
Files withARGYRES DIMITRI9NETLOGIC MICROSYSTEMS INC7HEWLETT PACKARD DEVELOPMENT CO5HEWLETT PACKARD CO2KRISHNAMURTHY GANESH1
Top patents by PatentIndex Score
24 records- 0198US8462532B1Fast quaternary content addressable memory cellARGYRES DIMITRI·Filed 2011·Granted Jun 11, 2013·422 cites·17 claims
- 0294US8582338B1Ternary content addressable memory cell having single transistor pull-down stackARGYRES DIMITRI·Filed 2011·Granted Nov 12, 2013·23 cites·21 claims
- 0394US7589362B1Configurable non-volatile logic structure for characterizing an integrated circuit deviceNETLOGIC MICROSYSTEMS INC·Filed 2007·Granted Sep 15, 2009·26 cites·26 claims
- 0494US5644342AAddressing system for an integrated printheadHEWLETT PACKARD CO·Filed 1995·Granted Jul 1, 1997·103 cites·20 claims
- 0591US8625320B1Quaternary content addressable memory cell having one transistor pull-down stackARGYRES DIMITRI·Filed 2011·Granted Jan 7, 2014·15 cites·21 claims
- 0691US7050318B1Selective match line pre-charging in a CAM device using pre-compare operationsNETLOGIC MICROSYSTEMS INC·Filed 2004·Granted May 23, 2006·62 cites·72 claims
- 0788US8675798B1Systems, circuits, and methods for phase inversionARGYRES DIMITRI·Filed 2010·Granted Mar 18, 2014·9 cites·20 claims
- 0888US8619451B1Power savings in a content addressable memory device using masked pre-compare operationsARGYRES DIMITRI·Filed 2012·Granted Dec 31, 2013·10 cites·32 claims
- 0988US8553441B1Ternary content addressable memory cell having two transistor pull-down stackARGYRES DIMITRI·Filed 2011·Granted Oct 8, 2013·12 cites·17 claims
- 1086US8837188B1Content addressable memory row having virtual ground and charge sharingKRISHNAMURTHY GANESH·Filed 2011·Granted Sep 16, 2014·18 cites·35 claims
- 1184US8493763B1Self-timed match line cascading in a partitioned content addressable memory arrayARGYRES DIMITRI·Filed 2011·Granted Jul 23, 2013·9 cites·30 claims
- 1277US7412561B2Transposing of bits in input data to form a comparand within a content addressable memoryNETLOGIC MICROSYSTEMS INC·Filed 2004·Granted Aug 12, 2008·18 cites·22 claims
- 1376US9019737B2Power savings in a content addressable memory device using masked pre-compare operationsNETLOGIC MICROSYSTEMS INC·Filed 2013·Granted Apr 28, 2015·4 cites·20 claims
- 1468US6564365B1Method of simultaneously displaying schematic and timing dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted May 13, 2003·11 cites·20 claims
- 1564US7868383B2Configurable non-volatile logic structure for characterizing an integrated circuit deviceNETLOGIC MICROSYSTEMS INC·Filed 2009·Granted Jan 11, 2011·2 cites·12 claims
- 1663US8638582B1Content addressable memory with base-three numeral systemARGYRES DIMITRI·Filed 2011·Granted Jan 28, 2014·2 cites·26 claims
- 1760US6964028B2Method of simultaneously displaying schematic and timing dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Nov 8, 2005·6 cites·20 claims
- 1857US6591404B1Method of automatically finding and fixing min-time violationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jul 8, 2003·4 cites·20 claims
- 1951US6715137B2Method of resolving min-time violations in an integrated circuitHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 30, 2004·1 cites·21 claims
- 2046US9123417B1Content addressable memory with base-three numeral systemNETLOGIC MICROSYSTEMS INC·Filed 2013·Granted Sep 1, 2015·0 cites·19 claims
- 2143US7856524B2Transposing of bits in input data to form a comparand within a content addressable memoryNETLOGIC MICROSYSTEMS INC·Filed 2008·Granted Dec 21, 2010·0 cites·6 claims
- 2240US6861876B1Pulse evaluate logic-latchHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 1, 2005·1 cites·10 claims
- 2339US8773880B2Content addressable memory array having virtual ground nodesARGYRES DIMITRI·Filed 2011·Granted Jul 8, 2014·0 cites·18 claims
- 2439US6317379B1Determine output of a read/write portHEWLETT PACKARD CO·Filed 2000·Granted Nov 13, 2001·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →