Inventor · disambiguated record
Dinesh D. Gaitonde
Also filed as: GAITONDE DINESH · GAITONDE DINESH D
24 granted patents·4 pending applications·327 citations·filing 1997–2023
95Inventor score
Files withXILINX INC23MONTEREY DESIGN SYSTEMS INC2GAITONDE DINESH D1MOTOROLA INC1RAJE SALIL RAVINDRA1
Top patents by PatentIndex Score
28 records- 0194US10838908B2Configurable network-on-chip for a programmable deviceXILINX INC·Filed 2018·Granted Nov 17, 2020·12 cites·20 claims
- 0292US10628547B1Routing circuit designs for implementation using a programmable network on chipXILINX INC·Filed 2017·Granted Apr 21, 2020·10 cites·18 claims
- 0391US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 0490US12079484B2Random reads using multi-port memory and on-chip memory blocksXILINX INC·Filed 2023·Granted Sep 3, 2024·1 cites·20 claims
- 0589US10565346B1Placement, routing, and deadlock removal for network-on-chip using integer linear programmingXILINX INC·Filed 2017·Granted Feb 18, 2020·9 cites·20 claims
- 0685US10614191B1Performing placement and routing concurrentlyXILINX INC·Filed 2018·Granted Apr 7, 2020·4 cites·20 claims
- 0785US8937491B2Clock network architectureXILINX INC·Filed 2012·Granted Jan 20, 2015·8 cites·19 claims
- 0881US10747929B1Resolving timing violations in multi-die circuit designsXILINX INC·Filed 2019·Granted Aug 18, 2020·3 cites·20 claims
- 0981US8024696B1Clock speed for a digital circuitXILINX INC·Filed 2008·Granted Sep 20, 2011·11 cites·20 claims
- 1078US11681846B1Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designsXILINX INC·Filed 2021·Granted Jun 20, 2023·1 cites·4 claims
- 1177US10503861B1Placing and routing an interface portion and a main portion of a circuit designXILINX INC·Filed 2018·Granted Dec 10, 2019·3 cites·20 claims
- 1276US8219957B1Global placement legalization for complex packing rulesGAITONDE DINESH D·Filed 2010·Granted Jul 10, 2012·7 cites·17 claims
- 1374US7886256B1Timing analysis of a mapped logic design using physical delaysXILINX INC·Filed 2008·Granted Feb 8, 2011·7 cites·20 claims
- 1470US12411168B2Software defined device variantsXILINX INC·Filed 2023·Granted Sep 9, 2025·0 cites·20 claims
- 1567US11720255B1Random reads using multi-port memory and on-chip memory blocksXILINX INC·Filed 2021·Granted Aug 8, 2023·0 cites·20 claims
- 1666US12461877B23D stacked device having improved data flowXILINX INC·Filed 2023·Granted Nov 4, 2025·0 cites·20 claims
- 1766US11263169B2Configurable network-on-chip for a programmable deviceXILINX INC·Filed 2020·Granted Mar 1, 2022·0 cites·20 claims
- 1865US7594212B1Automatic pin placement for integrated circuits to aid circuit board designXILINX INC·Filed 2007·Granted Sep 22, 2009·3 cites·20 claims
- 1964US6775808B1Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuitsMONTEREY DESIGN SYSTEMS INC·Filed 2000·Granted Aug 10, 2004·13 cites·34 claims
- 2056US5940779AArchitectural power estimation method and apparatusMOTOROLA INC·Filed 1997·Granted Aug 17, 1999·33 cites·20 claims
- 2153US11888693B2Time-division multiplexing (TDM) in integrated circuits for routability and runtime enhancementXILINX INC·Filed 2022·Granted Jan 30, 2024·0 cites·20 claims
- 2252US10977404B1Dynamic scan chain and methodXILINX INC·Filed 2020·Granted Apr 13, 2021·0 cites·20 claims
- 2352US2024193227A1Compression of sparse matrices for vector processingXILINX INC·Filed 2022·Application pending·0 cites
- 2451US8972920B1Re-budgeting connections of a circuit designXILINX INC·Filed 2014·Granted Mar 3, 2015·0 cites·17 claims
- 2549US2023267169A1Sparse matrix dense vector multliplication circuitryXILINX INC·Filed 2022·Application pending·0 cites
- 2649US2024202423A1Runtime efficient multi-stage router flow for circuit designsXILINX INC·Filed 2022·Application pending·0 cites
- 2749US2024143891A1Multi-path routing in a network on chipXILINX INC·Filed 2022·Application pending·0 cites
- 2841US8667437B2Creating a standard cell circuit design from a programmable logic device circuit designRAJE SALIL RAVINDRA·Filed 2008·Granted Mar 4, 2014·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Dinesh D. Gaitonde files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →