Inventor · disambiguated record
Didier Louis
Also filed as: LOUIS DIDIER · LOUIS DIDIER R
13 granted patents·1 pending application·376 citations·filing 1992–2017
92Inventor score
Top patents by PatentIndex Score
14 records- 0191US9892066B1Dynamically adjusting read data return sizes based on interconnect bus utilizationIBM·Filed 2016·Granted Feb 13, 2018·7 cites·18 claims
- 0282US5621863ANeuron circuitIBM·Filed 1995·Granted Apr 15, 1997·159 cites·9 claims
- 0373US5701397ACircuit for pre-charging a free neuron circuitIBM·Filed 1995·Granted Dec 23, 1997·72 cites·7 claims
- 0472US10176125B2Dynamically adjusting read data return sizes based on interconnect bus utilizationIBM·Filed 2017·Granted Jan 8, 2019·1 cites·19 claims
- 0569US6748405B2Method and circuits for performing the quick search of the minimum/maximum value among a set of numbersIBM·Filed 2001·Granted Jun 8, 2004·16 cites·9 claims
- 0665US6523018B1Neural chip architecture and neural networks incorporated thereinIBM·Filed 1999·Granted Feb 18, 2003·47 cites·10 claims
- 0760US7947594B2Interconnection structure with low dielectric constantCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2004·Granted May 24, 2011·9 cites·11 claims
- 0852US8421230B2Microelectronic device provided with an array of elements made from a conductive polymer with a positive temperature coefficientLOUIS DIDIER·Filed 2010·Granted Apr 16, 2013·1 cites·16 claims
- 0950US6502083B1Neuron architecture having a dual structure and neural networks incorporating the sameIBM·Filed 1999·Granted Dec 31, 2002·24 cites·12 claims
- 1048US7825023B2Method of manufacturing an interconnection structureCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2007·Granted Nov 2, 2010·0 cites·19 claims
- 1147US5463574AApparatus for argument reduction in exponential computations of IEEE standard floating-point numbersIBM·Filed 1993·Granted Oct 31, 1995·22 cites·3 claims
- 1246US2010022082A1Method for making a nanotube-based electrical connection between two facing surfacesCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2008·Application pending·0 cites
- 1345US5337265AApparatus for executing add/sub operations between IEEE standard floating-point numbersIBM·Filed 1992·Granted Aug 9, 1994·18 cites·7 claims
- 1429US6535862B1Method and circuit for performing the integrity diagnostic of an artificial neural networkIBM·Filed 1999·Granted Mar 18, 2003·0 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →