Inventor · disambiguated record
Dmitry N. Denisenko
Also filed as: DENISENKO DMITRY · DENISENKO DMITRY N · DENISENKO DMITRY NIKOLAI
13 granted patents·1 pending application·75 citations·filing 2011–2020
90Inventor score
Top patents by PatentIndex Score
14 records- 0190US9166597B1Integrated circuit processing via offload processorALTERA CORP·Filed 2014·Granted Oct 20, 2015·11 cites·20 claims
- 0289US10558437B1Method and apparatus for performing profile guided optimization for high-level synthesisALTERA CORP·Filed 2013·Granted Feb 11, 2020·13 cites·21 claims
- 0387US9819841B1Integrated circuits with optical flow computation circuitryALTERA CORP·Filed 2015·Granted Nov 14, 2017·6 cites·18 claims
- 0486US8806403B1Efficient configuration of an integrated circuit device using high-level languageALTERA CORP·Filed 2013·Granted Aug 12, 2014·9 cites·20 claims
- 0586US8627261B1Method and apparatus for performing automatic decoupling capacitor selection for power distribution networksOISHEI ANDREW E·Filed 2011·Granted Jan 7, 2014·15 cites·20 claims
- 0684US11361133B2Method of reporting circuit performance for high-level synthesisINTEL CORP·Filed 2017·Granted Jun 14, 2022·4 cites·20 claims
- 0784US9529950B1Systems and methods for performing profile-based circuit optimization using high-level system modelingALTERA CORP·Filed 2015·Granted Dec 27, 2016·9 cites·23 claims
- 0872US9626218B1Repartitioning and reordering of multiple threads into subsets based on possible access conflict, for sequential access to groups of memory banks in a shared memoryALTERA CORP·Filed 2014·Granted Apr 18, 2017·3 cites·20 claims
- 0968US9582628B1Method and apparatus for performing automatic decoupling capacitor selection for power distribution networksALTERA CORP·Filed 2013·Granted Feb 28, 2017·2 cites·19 claims
- 1068US9547738B1Invariant code optimization in high-level FPGA synthesisALTERA CORP·Filed 2014·Granted Jan 17, 2017·2 cites·17 claims
- 1162US10474441B1Method and apparatus for performing automatic data compression algorithm selection during high-level compilationALTERA CORP·Filed 2013·Granted Nov 12, 2019·1 cites·27 claims
- 1257US2020225922A1Method and apparatus for performing profile guided optimization for high-level synthesisALTERA CORP·Filed 2020·Application pending·0 cites
- 1354US10871946B2Methods for using a multiplier to support multiple sub-multiplication operationsINTEL CORP·Filed 2018·Granted Dec 22, 2020·0 cites·24 claims
- 1439US10303831B1Method and apparatus for performing and utilizing source code area annotationALTERA CORP·Filed 2015·Granted May 28, 2019·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →