Inventor · disambiguated record
Donald C. Boothroyd
Also filed as: BOOTHROYD DONALD C
14 granted patents·237 citations·filing 1982–1994
93Inventor score
Top patents by PatentIndex Score
14 records- 0165US5435000ACentral processing unit using dual basic processing units and combined result busBULL HN INFORMATION SYST·Filed 1993·Granted Jul 18, 1995·46 cites·12 claims
- 0264US4583199AApparatus for aligning and packing a first operand into a second operand of a different character sizeHONEYWELL INF SYSTEMS·Filed 1982·Granted Apr 15, 1986·30 cites·4 claims
- 0358US4598365APipelined decimal character execution unitHONEYWELL INF SYSTEMS·Filed 1983·Granted Jul 1, 1986·24 cites·29 claims
- 0456US4620274AData available indicator for an exhausted operand stringHONEYWELL INF SYSTEMS·Filed 1983·Granted Oct 28, 1986·22 cites·4 claims
- 0552US4608633AMethod for decreasing execution time of numeric instructionsHONEYWELL INF SYSTEMS·Filed 1983·Granted Aug 26, 1986·18 cites·1 claims
- 0652US4575795AApparatus for detecting a predetermined character of a data stringHONEYWELL INF SYSTEMS·Filed 1983·Granted Mar 11, 1986·18 cites·5 claims
- 0750US5440724ACentral processing unit using dual basic processing units and combined result bus and incorporating means for obtaining access to internal BPU test signalsBULL HN INFORMATION SYST·Filed 1993·Granted Aug 8, 1995·16 cites·3 claims
- 0849US4611278AWraparound buffer for repetitive decimal numeric operationsHONEYWELL INF SYSTEMS·Filed 1983·Granted Sep 9, 1986·17 cites·2 claims
- 0947US5251321ABinary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unitBULL HN INFORMATION SYST·Filed 1992·Granted Oct 5, 1993·20 cites·4 claims
- 1043US4598359AApparatus for forward or reverse reading of multiple variable length operandsHONEYWELL INF SYSTEMS·Filed 1983·Granted Jul 1, 1986·12 cites·4 claims
- 1132US4506345AData alignment circuitHONEYWELL INF SYSTEMS·Filed 1982·Granted Mar 19, 1985·5 cites·4 claims
- 1231US5515529ACentral processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor countBULL HN INFORMATION SYST·Filed 1994·Granted May 7, 1996·3 cites·5 claims
- 1330US5495579ACentral processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor countBULL HN INFORMATION SYST·Filed 1994·Granted Feb 27, 1996·2 cites·5 claims
- 1429US5422837AApparatus for detecting differences between double precision results produced by dual processing units operating in parallelBULL HN INFORMATION SYST·Filed 1993·Granted Jun 6, 1995·4 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →