Inventor · disambiguated record
Donald S. Gerber
Also filed as: GERBER DONALD · GERBER DONALD S
9 granted patents·2 pending applications·326 citations·filing 1990–2010
90Inventor score
Top patents by PatentIndex Score
11 records- 0190US5073230AMeans and methods of lifting and relocating an epitaxial device layerUNIV ARIZONA·Filed 1990·Granted Dec 17, 1991·212 cites·27 claims
- 0279US6222761B1Method for minimizing program disturb in a memory cellMICROCHIP TECH INC·Filed 2000·Granted Apr 24, 2001·25 cites·16 claims
- 0373US7466591B2Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuitsMICROCHIP TECH INC·Filed 2006·Granted Dec 16, 2008·6 cites·6 claims
- 0471US6432773B1Memory cell having an ONO film with an ONO sidewall and method of fabricating sameMICROCHIP TECH INC·Filed 1999·Granted Aug 13, 2002·34 cites·13 claims
- 0569US6236595B1Programming method for a memory cellMICROCHIP TECH INC·Filed 2000·Granted May 22, 2001·19 cites·13 claims
- 0667US6504191B2Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method thereforMICROCHIP TECH INC·Filed 2001·Granted Jan 7, 2003·11 cites·13 claims
- 0759US7817474B2Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuitsMICROCHIP TECH INC·Filed 2008·Granted Oct 19, 2010·3 cites·19 claims
- 0857US6300183B1Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method thereforMICROCHIP TECH INC·Filed 1999·Granted Oct 9, 2001·14 cites·6 claims
- 0955US8094503B2Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuitsSHIELDS JEFFREY A·Filed 2010·Granted Jan 10, 2012·2 cites·9 claims
- 1033US2007140008A1Independently programmable memory segments within an NMOS electrically erasable programmable read only memory array achieved by P-well separation and method thereforMICROCHIP TECH INC·Filed 2005·Application pending·0 cites
- 1133US2002006059A1Method for minimizing program disturb in a memory cellFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →