Inventor · disambiguated record
Donald F. Hooper
Also filed as: HOOPER DONALD · HOOPER DONALD F
63 granted patents·5 pending applications·4,693 citations·filing 1983–2009
99Inventor score
Top patents by PatentIndex Score
68 records- 0198US5442390AVideo on demand with memory accessing and or like functionsDIGITAL EQUIPMENT CORP·Filed 1993·Granted Aug 15, 1995·692 cites·10 claims
- 0298US5414455ASegmented video on demand systemDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 9, 1995·818 cites·29 claims
- 0395US7181742B2Allocation of packets and threadsINTEL CORP·Filed 2002·Granted Feb 20, 2007·117 cites·26 claims
- 0495US5493638ARemote display of an image by transmitting compressed video frames representing back-ground and overlay portions thereofDIGITAL EQUIPMENT CORP·Filed 1994·Granted Feb 20, 1996·291 cites·22 claims
- 0593US6625654B1Thread signaling in multi-threaded network processorINTEL CORP·Filed 1999·Granted Sep 23, 2003·164 cites·16 claims
- 0693US5422674ARemote display of an image by transmitting compressed video frames representing background and overlay portions thereofDIGITAL EQUIPMENT CORP·Filed 1993·Granted Jun 6, 1995·204 cites·13 claims
- 0792US7434221B2Multi-threaded sequenced receive for fast network port stream of packetsINTEL CORP·Filed 2005·Granted Oct 7, 2008·26 cites·14 claims
- 0892US6668317B1Microengine for parallel processor architectureINTEL CORP·Filed 1999·Granted Dec 23, 2003·157 cites·41 claims
- 0991US6952824B1Multi-threaded sequenced receive for fast network port stream of packetsINTEL CORP·Filed 2000·Granted Oct 4, 2005·65 cites·7 claims
- 1091US5671225ADistributed interactive multimedia service systemDIGITAL EQUIPMENT CORP·Filed 1995·Granted Sep 23, 1997·347 cites·14 claims
- 1190US7546444B1Register set used in multithreaded parallel processor architectureINTEL CORP·Filed 2000·Granted Jun 9, 2009·59 cites·20 claims
- 1290US6947425B1Multi-threaded sequenced transmit software for packet forwarding deviceINTEL CORP·Filed 2000·Granted Sep 20, 2005·59 cites·22 claims
- 1390US6611276B1Graphical user interface that displays operation of processor threads over timeINTEL CORP·Filed 1999·Granted Aug 26, 2003·152 cites·28 claims
- 1489US7111296B2Thread signaling in multi-threaded processorINTEL CORP·Filed 2003·Granted Sep 19, 2006·45 cites·27 claims
- 1588US7111071B1Longest prefix match for IP routersINTEL CORP·Filed 2000·Granted Sep 19, 2006·60 cites·15 claims
- 1688US7020871B2Breakpoint method for parallel hardware threads in multithreaded processorINTEL CORP·Filed 2000·Granted Mar 28, 2006·62 cites·12 claims
- 1787US7100102B2Method and apparatus for performing cyclic redundancy checksINTEL CORP·Filed 2003·Granted Aug 29, 2006·23 cites·27 claims
- 1887US6661794B1Method and apparatus for gigabit packet assignment for multithreaded packet processingINTEL CORP·Filed 1999·Granted Dec 9, 2003·135 cites·27 claims
- 1986US7191321B2Microengine for parallel processor architectureINTEL CORP·Filed 2003·Granted Mar 13, 2007·38 cites·22 claims
- 2086US5150308AParameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designsDIGITAL EQUIPMENT CORP·Filed 1989·Granted Sep 22, 1992·78 cites·6 claims
- 2185US5175696ARule structure in a procedure for synthesis of logic circuitsDIGITAL EQUIPMENT CORP·Filed 1991·Granted Dec 29, 1992·68 cites·12 claims
- 2284US7248584B2Network packet processingINTEL CORP·Filed 2002·Granted Jul 24, 2007·41 cites·28 claims
- 2384US7126952B2Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion methodINTEL CORP·Filed 2001·Granted Oct 24, 2006·44 cites·31 claims
- 2484US5267175AData base access mechanism for rules utilized by a synthesis procedure for logic circuit designDIGITAL EQUIPMENT CORP·Filed 1993·Granted Nov 30, 1993·104 cites·17 claims
- 2584US5212650AProcedure and data structure for synthesis and transformation of logic circuit designsDIGITAL EQUIPMENT CORP·Filed 1989·Granted May 18, 1993·85 cites·33 claims
- 2682US6944850B2Hop method for stepping parallel hardware threadsINTEL CORP·Filed 2000·Granted Sep 13, 2005·39 cites·14 claims
- 2781US7006495B2Transmitting multicast data packetsINTEL CORP·Filed 2001·Granted Feb 28, 2006·33 cites·24 claims
- 2880US7158964B2Queue managementINTEL CORP·Filed 2001·Granted Jan 2, 2007·28 cites·31 claims
- 2980US7124196B2Processing a network packet using queuesINTEL CORP·Filed 2002·Granted Oct 17, 2006·30 cites·28 claims
- 3080US5819282ADatabase generatorDIGITAL EQUIPMENT CORP·Filed 1996·Granted Oct 6, 1998·91 cites·46 claims
- 3179US7991983B2Register set used in multithreaded parallel processor architectureINTEL CORP·Filed 2009·Granted Aug 2, 2011·7 cites·22 claims
- 3279US7443836B2Processing a data packetINTEL CORP·Filed 2003·Granted Oct 28, 2008·28 cites·26 claims
- 3379US7433307B2Flow control in a network environmentINTEL CORP·Filed 2002·Granted Oct 7, 2008·26 cites·52 claims
- 3479US7206858B2DSL transmit traffic shaper structure and procedureINTEL CORP·Filed 2002·Granted Apr 17, 2007·34 cites·68 claims
- 3578US7684970B2Graphical user interface for use during processor simulationINTEL CORP·Filed 2004·Granted Mar 23, 2010·25 cites·10 claims
- 3677US7751402B2Method and apparatus for gigabit packet assignment for multithreaded packet processingINTEL CORP·Filed 2003·Granted Jul 6, 2010·18 cites·20 claims
- 3776US7480706B1Multi-threaded round-robin receive for fast network portINTEL CORP·Filed 2000·Granted Jan 20, 2009·23 cites·16 claims
- 3876US7096277B2Distributed lookup based on packet contentsINTEL CORP·Filed 2002·Granted Aug 22, 2006·21 cites·25 claims
- 3975US7352769B2Multiple calendar schedule reservation structure and methodINTEL CORP·Filed 2002·Granted Apr 1, 2008·24 cites·48 claims
- 4073US6668311B2Method for memory allocation and management using push/pop apparatusINTEL CORP·Filed 2001·Granted Dec 23, 2003·15 cites·23 claims
- 4170US7082104B2Network device switchINTEL CORP·Filed 2001·Granted Jul 25, 2006·18 cites·15 claims
- 4270US5222029ABitwise implementation mechanism for a circuit design synthesis procedureDIGITAL EQUIPMENT CORP·Filed 1992·Granted Jun 22, 1993·55 cites·7 claims
- 4368US6684395B2Multiple image dynamic bind and load procedure for a multi-processorINTEL CORP·Filed 2000·Granted Jan 27, 2004·15 cites·15 claims
- 4466US7343563B2Graphical user interfaceINTEL CORP·Filed 2003·Granted Mar 11, 2008·10 cites·17 claims
- 4566US7336606B2Circular link list schedulingINTEL CORP·Filed 2003·Granted Feb 26, 2008·11 cites·22 claims
- 4666US7240164B2Folding for a multi-threaded network processorINTEL CORP·Filed 2003·Granted Jul 3, 2007·11 cites·29 claims
- 4765US7328429B2Instruction operand tracing for software debugINTEL CORP·Filed 2003·Granted Feb 5, 2008·11 cites·22 claims
- 4865US6823438B2Method for memory allocation and management using push/pop apparatusINTEL CORP·Filed 2003·Granted Nov 23, 2004·8 cites·16 claims
- 4965US5168455AProcedure for incorporating timing parameters in the synthesis of logic circuit designsDIGITAL EQUIPMENT CORP·Filed 1991·Granted Dec 1, 1992·44 cites·17 claims
- 5064US7515588B2Method and apparatus to support a large internet protocol forwarding information baseINTEL CORP·Filed 2004·Granted Apr 7, 2009·10 cites·23 claims
Showing the top 50 of 68 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →