Inventor · disambiguated record
Do Soo Jeong
Also filed as: JEONG DO SOO
9 granted patents·1 pending application·1,144 citations·filing 1996–2002
92Inventor score
Technology areasH10W
Top patents by PatentIndex Score
10 records- 0196US5744827AThree dimensional stack package device having exposed coupling lead portions and vertical interconnection elementsSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Apr 28, 1998·312 cites·28 claims
- 0294US6087722AMulti-chip packageSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Jul 11, 2000·260 cites·11 claims
- 0393US6229205B1Semiconductor device package having twice-bent tie bar and small die padSAMSUNG ELECTRONICS CO LTD·Filed 1998·Granted May 8, 2001·208 cites·13 claims
- 0491US6013946AWire bond packages for semiconductor chips and related methods and assembliesSAMSUNG ELECTRONICS CO LTD·Filed 1997·Granted Jan 11, 2000·142 cites·25 claims
- 0590US5804874AStacked chip package device employing a plurality of lead on chip type semiconductor chipsSAMSUNG ELECTRONICS CO LTD·Filed 1997·Granted Sep 8, 1998·146 cites·12 claims
- 0672US5894107AChip-size package (CSP) using a multi-layer laminated lead frameSAMSUNG ELECTRONICS CO LTD·Filed 1997·Granted Apr 13, 1999·47 cites·9 claims
- 0755US6319828B1Method for manufacturing a chip scale package having copper traces selectively plated with goldSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Nov 20, 2001·18 cites·14 claims
- 0842US5811875ALead frames including extended tie-bars, and semiconductor chip packages using sameSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Sep 22, 1998·11 cites·13 claims
- 0937US2002048951A1Method for manufacturing a chip scale packageFiled 2001·Application pending·0 cites
- 1028US6707142B2Package stacked semiconductor device having pin linking meansBARUN ELECTRONICS CO LTD·Filed 2002·Granted Mar 16, 2004·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →