Inventor · disambiguated record
Dominik Lubeley
Also filed as: LUBELEY DOMINIK
20 granted patents·9 pending applications·5 citations·filing 2015–2025
87Inventor score
Files withDSPACE GMBH29
Top patents by PatentIndex Score
29 records- 0181US9870440B2Method for automatically generating a netlist of an FPGA programDSPACE GMBH·Filed 2015·Granted Jan 16, 2018·4 cites·21 claims
- 0268US10394989B2Method for creating an FPGA netlistDSPACE GMBH·Filed 2017·Granted Aug 27, 2019·1 cites·15 claims
- 0364US12348236B2Method for changing a bitwidth of an FPGA configurationDSPACE GMBH·Filed 2022·Granted Jul 1, 2025·0 cites·12 claims
- 0457US2025021462A1Method for fpga build and initializationDSPACE GMBH·Filed 2024·Application pending·0 cites
- 0556US2025260405A1Programmable gate array and method of generating configuration data for programming a gate arrayDSPACE GMBH·Filed 2025·Application pending·0 cites
- 0655US12197336B2Method for effectively increasing a memory on an FPGADSPACE GMBH·Filed 2023·Granted Jan 14, 2025·0 cites·15 claims
- 0753US12253876B2Method for programming an FPGADSPACE GMBH·Filed 2023·Granted Mar 18, 2025·0 cites·12 claims
- 0853US12079601B2Computer-implemented method for creating a hierarchical block diagramDSPACE GMBH·Filed 2022·Granted Sep 3, 2024·0 cites·14 claims
- 0953US11187748B2Procedure for reviewing an FPGA-programDSPACE GMBH·Filed 2019·Granted Nov 30, 2021·0 cites·14 claims
- 1053US10706196B2Incremental generation of an FPGA implementation with a graph-based similarity searchDSPACE GMBH·Filed 2018·Granted Jul 7, 2020·0 cites·16 claims
- 1153US2024028457A1Method and device for detecting errors in routes and calculations within an fpgaDSPACE GMBH·Filed 2023·Application pending·0 cites
- 1252US12341512B2Method for programming an FPGADSPACE GMBH·Filed 2022·Granted Jun 24, 2025·0 cites·10 claims
- 1350US11586793B2Method for producing an association listDSPACE GMBH·Filed 2018·Granted Feb 21, 2023·0 cites·11 claims
- 1450US11222159B2Method, computer-based system and computer program product for planning partitions for a programmable gate arrayDSPACE GMBH·Filed 2021·Granted Jan 11, 2022·0 cites·13 claims
- 1550US2023333892A1Method for documenting computing steps of a real time system executed on a computer core of a processor, processor and real time systemDSPACE GMBH·Filed 2023·Application pending·0 cites
- 1647US2023082540A1Method of adding another circuit componentDSPACE GMBH·Filed 2022·Application pending·0 cites
- 1747US2024176938A1Method for preparing and providing an fpga build result of an fpga modelDSPACE GMBH·Filed 2023·Application pending·0 cites
- 1846US12158849B2Method for data communication between subregions of an FPGADSPACE GMBH·Filed 2022·Granted Dec 3, 2024·0 cites·14 claims
- 1945US12265771B2Method for dividing simulation models up between a processor and an FPGADSPACE GMBH·Filed 2022·Granted Apr 1, 2025·0 cites·15 claims
- 2045US12124290B2Time-synchronized input and/or output of signals with a selectable sampling rateDSPACE GMBH·Filed 2021·Granted Oct 22, 2024·0 cites·15 claims
- 2145US11843514B2Computer-implemented method for restructuring a predefined distributed real-time simulation networkDSPACE GMBH·Filed 2021·Granted Dec 12, 2023·0 cites·18 claims
- 2244US10224930B2Method for detecting the topology of electrical wiringDSPACE GMBH·Filed 2018·Granted Mar 5, 2019·0 cites·14 claims
- 2343US2019138310A1Method for reading out variables from an fpgaDSPACE GMBH·Filed 2018·Application pending·0 cites
- 2442US11017141B2Method for troubleshooting the program logic of a system of distributed progammable gate arraysDSPACE GMBH·Filed 2020·Granted May 25, 2021·0 cites·12 claims
- 2540US11442884B2Method for programming a programmable gate array in a distributed computer systemDSPACE GMBH·Filed 2021·Granted Sep 13, 2022·0 cites·17 claims
- 2639US9628085B1Method and device for accelerated access to signals of a programmable logic deviceDSPACE GMBH·Filed 2016·Granted Apr 18, 2017·0 cites·10 claims
- 2739US2017329732A1Method for temporally synchronizing the output and/or temporally synchronizing the processing of signalsDSPACE GMBH·Filed 2017·Application pending·0 cites
- 2838US10102325B2Method for determining the power consumption of a programmable logic deviceDSPACE GMBH·Filed 2016·Granted Oct 16, 2018·0 cites·18 claims
- 2938US2020145486A1Computer network with a first and a second synchronizing signal transmitterDSPACE GMBH·Filed 2019·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →