Inventor · disambiguated record
Donald D. Parker
Also filed as: PARKER DONALD D
17 granted patents·722 citations·filing 1979–2001
96Inventor score
Top patents by PatentIndex Score
17 records- 0197US6601121B2Quad pumped bus architecture and protocolINTEL CORP·Filed 2001·Granted Jul 29, 2003·104 cites·23 claims
- 0284US6041403AMethod and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstructionINTEL CORP·Filed 1996·Granted Mar 21, 2000·115 cites·34 claims
- 0383US6907487B2Enhanced highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Jun 14, 2005·22 cites·62 claims
- 0482US6804735B2Response and data phases in a highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Oct 12, 2004·21 cites·21 claims
- 0579US6880031B2Snoop phase in a highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Apr 12, 2005·18 cites·22 claims
- 0678US6807592B2Quad pumped bus architecture and protocolINTEL CORP·Filed 2001·Granted Oct 19, 2004·16 cites·25 claims
- 0778US5630083ADecoder for decoding multiple instructions in parallelINTEL CORP·Filed 1996·Granted May 13, 1997·88 cites·15 claims
- 0872US5600806AMethod and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction bufferINTEL CORP·Filed 1994·Granted Feb 4, 1997·50 cites·7 claims
- 0971US4302908ALivestock detaining gatePOWDER RIVER ENTERPRISES INC·Filed 1979·Granted Dec 1, 1981·26 cites·5 claims
- 1069US6609171B1Quad pumped bus architecture and protocolINTEL CORP·Filed 1999·Granted Aug 19, 2003·34 cites·64 claims
- 1168US5586277AMethod for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decodersINTEL CORP·Filed 1995·Granted Dec 17, 1996·56 cites·23 claims
- 1266US5566298AMethod for state recovery during assist and restart in a decoder having an alias mechanismINTEL CORP·Filed 1994·Granted Oct 15, 1996·50 cites·22 claims
- 1364US5673427APacking valid micro operations received from a parallel decoder into adjacent locations of an output queueINTEL CORP·Filed 1996·Granted Sep 30, 1997·45 cites·13 claims
- 1452US5822555AMethod and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction bufferINTEL CORP·Filed 1996·Granted Oct 13, 1998·22 cites·24 claims
- 1551US5581717ADecoding circuit and method providing immediate data for a micro-operation issued from a decoderINTEL CORP·Filed 1994·Granted Dec 3, 1996·22 cites·6 claims
- 1647US5559974ADecoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operationINTEL CORP·Filed 1995·Granted Sep 24, 1996·20 cites·16 claims
- 1742US5668985ADecoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queueINTEL CORP·Filed 1994·Granted Sep 16, 1997·13 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →