Inventor · disambiguated record
Douglas O. Powell
Also filed as: POWELL DOUGLAS O · POWELL DOUGLAS OLIVER
40 granted patents·3 pending applications·1,362 citations·filing 1990–2017
98Inventor score
Top patents by PatentIndex Score
43 records- 0198US7301108B2Multi-layered interconnect structure using liquid crystalline polymer dielectricIBM·Filed 2004·Granted Nov 27, 2007·105 cites·10 claims
- 0298US5487218AMethod for making printed circuit boards with selectivity filled plated through holesIBM·Filed 1994·Granted Jan 30, 1996·284 cites·2 claims
- 0396US8522430B2Clustered stacked vias for reliable electronic substratesKACKER KARAN·Filed 2012·Granted Sep 3, 2013·37 cites·8 claims
- 0496US6407341B1Conductive substructures of a multilayered laminateIBM·Filed 2000·Granted Jun 18, 2002·138 cites·3 claims
- 0594US5557844AMethod of preparing a printed circuit boardIBM·Filed 1995·Granted Sep 24, 1996·138 cites·1 claims
- 0694US5185073AMethod of fabricating nendritic materialsIBM·Filed 1991·Granted Feb 9, 1993·173 cites·4 claims
- 0792US6931723B1Organic dielectric electronic interconnect structures and method for makingIBM·Filed 2000·Granted Aug 23, 2005·47 cites·57 claims
- 0892US6826830B2Multi-layered interconnect structure using liquid crystalline polymer dielectricIBM·Filed 2002·Granted Dec 7, 2004·42 cites·15 claims
- 0991US5137461ASeparable electrical connection technologyIBM·Filed 1990·Granted Aug 11, 1992·134 cites·8 claims
- 1084US6764748B1Z-interconnections with liquid crystal polymer dielectric filmsIBM·Filed 2003·Granted Jul 20, 2004·48 cites·10 claims
- 1183US9105535B2Copper feature design for warpage control of substratesBLACKSHEAR EDMUND·Filed 2012·Granted Aug 11, 2015·6 cites·8 claims
- 1282US9543255B2Reduced-warpage laminate structureIBM·Filed 2016·Granted Jan 10, 2017·3 cites·1 claims
- 1382US7253512B2Organic dielectric electronic interconnect structures and method for makingIBM·Filed 2005·Granted Aug 7, 2007·10 cites·18 claims
- 1481US9659131B2Copper feature design for warpage control of substratesGLOBALFOUNDRIES INC·Filed 2015·Granted May 23, 2017·3 cites·11 claims
- 1580US8791372B2Reducing impedance discontinuity in packagesHARVEY PAUL M·Filed 2012·Granted Jul 29, 2014·4 cites·16 claims
- 1679US6518516B2Multilayered laminateIBM·Filed 2002·Granted Feb 11, 2003·24 cites·17 claims
- 1778US8440917B2Method and apparatus to reduce impedance discontinuity in packagesHARVEY PAUL M·Filed 2007·Granted May 14, 2013·7 cites·13 claims
- 1876US7981245B2Multi-layered interconnect structure using liquid crystalline polymer dielectricIBM·Filed 2007·Granted Jul 19, 2011·4 cites·11 claims
- 1976US7777136B2Multi-layered interconnect structure using liquid crystalline polymer dielectricIBM·Filed 2007·Granted Aug 17, 2010·5 cites·11 claims
- 2074US5672260AProcess for selective application of solder to circuit packagesIBM·Filed 1996·Granted Sep 30, 1997·37 cites·11 claims
- 2174US5597469AProcess for selective application of solder to circuit packagesIBM·Filed 1995·Granted Jan 28, 1997·37 cites·7 claims
- 2273US9613915B2Reduced-warpage laminate structureIBM·Filed 2014·Granted Apr 4, 2017·2 cites·16 claims
- 2371US6423905B1Printed wiring board with improved plated through hole fatigue lifeIBM·Filed 2000·Granted Jul 23, 2002·15 cites·6 claims
- 2469US8242593B2Clustered stacked vias for reliable electronic substratesKACKER KARAN·Filed 2008·Granted Aug 14, 2012·4 cites·8 claims
- 2567US9478453B2Sacrificial carrier dicing of semiconductor wafersIBM·Filed 2014·Granted Oct 25, 2016·1 cites·16 claims
- 2662US6492715B1Integrated semiconductor packageIBM·Filed 2000·Granted Dec 10, 2002·10 cites·9 claims
- 2761US6832436B2Method for forming a substructure of a multilayered laminateIBM·Filed 2002·Granted Dec 21, 2004·8 cites·19 claims
- 2860US6790305B2Method and structure for small pitch z-axis electrical interconnectionsIBM·Filed 2002·Granted Sep 14, 2004·8 cites·9 claims
- 2958US7786579B2Apparatus for crack prevention in integrated circuit packagesIBM·Filed 2007·Granted Aug 31, 2010·1 cites·4 claims
- 3057US9099458B2Construction of reliable stacked via in electronic substrates—vertical stiffness control methodKACKER KARAN·Filed 2012·Granted Aug 4, 2015·0 cites·13 claims
- 3157US8866026B2Construction of reliable stacked via in electronic substrates—vertical stiffness control methodKACKER KARAN·Filed 2012·Granted Oct 21, 2014·0 cites·11 claims
- 3257US7128256B2Z-interconnections with liquid crystal polymer dielectric filmsIBM·Filed 2004·Granted Oct 31, 2006·0 cites·10 claims
- 3355US10685919B2Reduced-warpage laminate structureIBM·Filed 2017·Granted Jun 16, 2020·0 cites·9 claims
- 3455US8258410B2Construction of reliable stacked via in electronic substrates—vertical stiffness control methodKACKER KARAN·Filed 2008·Granted Sep 4, 2012·0 cites·4 claims
- 3555US6955849B2Method and structure for small pitch z-axis electrical interconnectionsIBM·Filed 2004·Granted Oct 18, 2005·5 cites·9 claims
- 3655US2010218891A1Multi-layered interconnect structure using liquid crystalline polymer dielectricIBM·Filed 2010·Application pending·0 cites
- 3753US7083901B2Joining member for Z-interconnect in electronic devices without conductive pasteIBM·Filed 2002·Granted Aug 1, 2006·4 cites·28 claims
- 3852US5656139AElectroplating apparatusIBM·Filed 1996·Granted Aug 12, 1997·13 cites·6 claims
- 3950US9484239B2Sacrificial carrier dicing of semiconductor wafersIBM·Filed 2015·Granted Nov 1, 2016·0 cites·9 claims
- 4050US2009265028A1Organic Substrate with Asymmetric Thickness for Warp MitigationIBM·Filed 2008·Application pending·0 cites
- 4145US2009189289A1Embedded constrainer discs for reliable stacked vias in electronic substratesIBM·Filed 2008·Application pending·0 cites
- 4239US8756546B2Elastic modulus mapping of a chip carrier in a flip chip packageCOHEN ERWIN B·Filed 2012·Granted Jun 17, 2014·0 cites·5 claims
- 4338USRE37840EMethod of preparing a printed circuit boardIBM·Filed 1998·Granted Sep 17, 2002·5 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →