Inventor · disambiguated record
Douglas Sudjian
Also filed as: SUDJIAN DOUGLAS
13 granted patents·1 pending application·287 citations·filing 1996–2009
93Inventor score
Files withCYPRESS SEMICONDUCTOR CORP3IRF SEMICONDUCTOR INC2MICRO LINEAR CORP2RESONEXT COMMUNICATIONS INC2SUDJIAN DOUGLAS2
Top patents by PatentIndex Score
14 records- 0196US7521976B1Low power high speed latch for a prescaler dividerNANOAMP SOLUTIONS INC·Filed 2005·Granted Apr 21, 2009·57 cites·31 claims
- 0285US6633073B2Method and apparatus for isolating circuits using deep substrate n-wellRF MICRO DEVICES INC·Filed 2001·Granted Oct 14, 2003·68 cites·21 claims
- 0384US6774689B1Triple input phase detector and methodology for setting delay between two sets of phase outputsCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Aug 10, 2004·34 cites·13 claims
- 0482US7409027B1System and method for recovering a clock using a reduced rate linear phase detector and voltage controlled oscillatorCYPRESS SEMICONDUCTOR CORP·Filed 2006·Granted Aug 5, 2008·9 cites·10 claims
- 0580US8310279B2Comparator with hysteresisSUDJIAN DOUGLAS·Filed 2009·Granted Nov 13, 2012·12 cites·25 claims
- 0680US7015736B1Symmetric charge pumpIRF SEMICONDUCTOR INC·Filed 2004·Granted Mar 21, 2006·24 cites·18 claims
- 0771US8688060B2Detection circuit for overdrive conditions in a wireless deviceSUDJIAN DOUGLAS·Filed 2009·Granted Apr 1, 2014·5 cites·26 claims
- 0866US6211699B1High performance CML to CMOS converterMICRO LINEAR CORP·Filed 1999·Granted Apr 3, 2001·22 cites·15 claims
- 0963US6657466B1System and method for generating interleaved multi-phase outputs from a nested pair of phase locked loopsCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Dec 2, 2003·12 cites·19 claims
- 1060US6222423B1Voltage controlled ring oscillator delayMICRO LINEAR CORP·Filed 1999·Granted Apr 24, 2001·17 cites·25 claims
- 1154US6628145B1High-speed logic gateRESONEXT COMMUNICATIONS INC·Filed 2001·Granted Sep 30, 2003·7 cites·22 claims
- 1249US6737899B2High-speed latch with integrated gateRESONEXT COMMUNICATIONS INC·Filed 2001·Granted May 18, 2004·5 cites·19 claims
- 1348US5675291APhase-lock loop with reduced acquistion timeNAT SEMICONDUCTOR CORP·Filed 1996·Granted Oct 7, 1997·15 cites·5 claims
- 1438US2008191783A1Symmetric charge pump replica bias detectorIRF SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →