Inventor · disambiguated record
Dung Q. Nguyen
Also filed as: NGUYEN DUNG · NGUYEN DUNG Q · NGUYEN DUNG QUOC
243 granted patents·27 pending applications·1,301 citations·filing 1994–2023
99Inventor score
Files withIBM251ABERNATHY CHRISTOPHER M4ABERNATHY CHRISTOPHER MICHAEL2BISHOP JAMES WILSON2LE HUNG QUI2
Top patents by PatentIndex Score
270 records- 0198US11144319B1Redistribution of architected states for a processor register fileIBM·Filed 2020·Granted Oct 12, 2021·19 cites·20 claims
- 0297US11249757B1Handling and fusing load instructions in a processorIBM·Filed 2020·Granted Feb 15, 2022·6 cites·18 claims
- 0397US9720696B2Independent mapping of threadsIBM·Filed 2014·Granted Aug 1, 2017·30 cites·6 claims
- 0497US8108655B2Selecting fixed-point instructions to issue on load-store unitABERNATHY CHRISTOPHER MICHAEL·Filed 2009·Granted Jan 31, 2012·148 cites·20 claims
- 0596US9367322B1Age based fast instruction issueIBM·Filed 2015·Granted Jun 14, 2016·18 cites·20 claims
- 0695US11163571B1Fusion to enhance early address generation of load instructions in a microprocessorIBM·Filed 2020·Granted Nov 2, 2021·4 cites·20 claims
- 0795US8041928B2Information handling system with real and virtual load/store instruction issue queueIBM·Filed 2008·Granted Oct 18, 2011·46 cites·20 claims
- 0895US7877580B2Branch lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Jan 25, 2011·41 cites·9 claims
- 0993US10387147B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 20, 2019·7 cites·11 claims
- 1093US9870229B2Independent mapping of threadsIBM·Filed 2015·Granted Jan 16, 2018·8 cites·9 claims
- 1193US8046566B2Method to reduce power consumption of a register file with multi SMT supportIBM·Filed 2008·Granted Oct 25, 2011·39 cites·13 claims
- 1293US7395414B2Dynamic recalculation of resource vector at issue queue for steering of dependent instructionsIBM·Filed 2005·Granted Jul 1, 2008·31 cites·6 claims
- 1392US7689812B2Method and system for restoring register mapper states for an out-of-order microprocessorIBM·Filed 2007·Granted Mar 30, 2010·29 cites·18 claims
- 1492US7467325B2Processor instruction retry recoveryIBM·Filed 2005·Granted Dec 16, 2008·26 cites·12 claims
- 1592US7290261B2Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processorIBM·Filed 2003·Granted Oct 30, 2007·98 cites·19 claims
- 1690US8245018B2Processor register recovery after flush operationNGUYEN DUNG QUOC·Filed 2008·Granted Aug 14, 2012·25 cites·21 claims
- 1789US11941398B1Fast mapper restore for flush in processorIBM·Filed 2022·Granted Mar 26, 2024·1 cites·20 claims
- 1889US8521998B2Instruction tracking system for processorsABERNATHY CHRISTOPHER MICHAEL·Filed 2010·Granted Aug 27, 2013·12 cites·22 claims
- 1989US8380964B2Processor including age tracking of issue queue instructionsIBM·Filed 2009·Granted Feb 19, 2013·18 cites·14 claims
- 2088US9985656B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·7 cites·6 claims
- 2188US9524171B1Split-level history buffer in a computer processing unitIBM·Filed 2016·Granted Dec 20, 2016·4 cites·1 claims
- 2287US11392386B2Program counter (PC)-relative load and store addressing for fused instructionsIBM·Filed 2020·Granted Jul 19, 2022·2 cites·20 claims
- 2387US9928128B2In-pipe error scrubbing within a processor coreIBM·Filed 2016·Granted Mar 27, 2018·6 cites·15 claims
- 2487US9740620B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 22, 2017·5 cites·13 claims
- 2587US7254697B2Method and apparatus for dynamic modification of microprocessor instruction group at dispatchIBM·Filed 2005·Granted Aug 7, 2007·18 cites·14 claims
- 2686US10394565B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 27, 2019·3 cites·6 claims
- 2786US10223125B2Linkable issue queue parallel execution slice processing methodIBM·Filed 2018·Granted Mar 5, 2019·3 cites·20 claims
- 2886US10073699B2Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architectureIBM·Filed 2015·Granted Sep 11, 2018·5 cites·20 claims
- 2985US9489207B2Processor and method for partially flushing a dispatched instruction group including a mispredicted branchBURKY WILLIAM E·Filed 2009·Granted Nov 8, 2016·20 cites·16 claims
- 3085US9389870B1Age based fast instruction issueIBM·Filed 2015·Granted Jul 12, 2016·3 cites·1 claims
- 3185US9389867B2Speculative finish of instruction execution in a processor coreIBM·Filed 2015·Granted Jul 12, 2016·4 cites·6 claims
- 3285US7594096B2Load lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Sep 22, 2009·13 cites·20 claims
- 3384US11900116B1Loosely-coupled slice target file dataIBM·Filed 2021·Granted Feb 13, 2024·1 cites·20 claims
- 3484US11868773B2Inferring future value for speculative branch resolution in a microprocessorIBM·Filed 2022·Granted Jan 9, 2024·1 cites·20 claims
- 3584US9985655B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·6 cites·11 claims
- 3684US9870045B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2016·Granted Jan 16, 2018·3 cites·7 claims
- 3784US9639418B2Parity protection of a registerIBM·Filed 2015·Granted May 2, 2017·4 cites·20 claims
- 3884US8271765B2Managing instructions for more efficient load/store unit usageBOSE PRADIP·Filed 2009·Granted Sep 18, 2012·13 cites·13 claims
- 3984US7827443B2Processor instruction retry recoveryIBM·Filed 2008·Granted Nov 2, 2010·12 cites·19 claims
- 4083US11531548B1Fast perfect issue of dependent instructions in a distributed issue queue systemIBM·Filed 2021·Granted Dec 20, 2022·1 cites·20 claims
- 4183US11132198B2Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2019·Granted Sep 28, 2021·2 cites·25 claims
- 4283US11119772B2Check pointing of accumulator register results in a microprocessorIBM·Filed 2019·Granted Sep 14, 2021·3 cites·18 claims
- 4383US7631308B2Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessorsIBM·Filed 2005·Granted Dec 8, 2009·12 cites·3 claims
- 4483US7093106B2Register rename array with individual thread bits set upon allocation and cleared upon instruction completionIBM·Filed 2003·Granted Aug 15, 2006·43 cites·23 claims
- 4583US7000047B2Mechanism for effectively handling livelocks in a simultaneous multithreading processorIBM·Filed 2003·Granted Feb 14, 2006·36 cites·26 claims
- 4682US10936321B2Instruction chainingIBM·Filed 2019·Granted Mar 2, 2021·3 cites·20 claims
- 4782US10209995B2Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructionsIBM·Filed 2014·Granted Feb 19, 2019·5 cites·17 claims
- 4882US10073697B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2016·Granted Sep 11, 2018·2 cites·5 claims
- 4982US9921833B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2015·Granted Mar 20, 2018·3 cites·11 claims
- 5082US9747217B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 29, 2017·3 cites·7 claims
Showing the top 50 of 270 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Dung Q. Nguyen files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →