Inventor · disambiguated record
Dwain A. Hicks
Also filed as: HICKS DWAIN A · HICKS DWAIN ALAN
30 granted patents·533 citations·filing 1993–2020
97Inventor score
Technology areasG06F
Files withIBM30
Top patents by PatentIndex Score
30 records- 0193US10740248B2Methods and systems for predicting virtual addressIBM·Filed 2018·Granted Aug 11, 2020·10 cites·20 claims
- 0291US10621106B1Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)IBM·Filed 2018·Granted Apr 14, 2020·7 cites·20 claims
- 0386US11221963B2Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)IBM·Filed 2020·Granted Jan 11, 2022·2 cites·19 claims
- 0486US7302527B2Systems and methods for executing load instructions that avoid order violationsIBM·Filed 2004·Granted Nov 27, 2007·47 cites·32 claims
- 0582US11061810B2Virtual cache mechanism for program break point register exception handlingIBM·Filed 2019·Granted Jul 13, 2021·3 cites·18 claims
- 0682US5584013AHierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cacheIBM·Filed 1994·Granted Dec 10, 1996·88 cites·17 claims
- 0780US10915459B2Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizesIBM·Filed 2018·Granted Feb 9, 2021·2 cites·20 claims
- 0878US5581734AMultiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacityIBM·Filed 1993·Granted Dec 3, 1996·82 cites·13 claims
- 0973US6085291ASystem and method for selectively controlling fetching and prefetching of data to a processorIBM·Filed 1995·Granted Jul 4, 2000·67 cites·20 claims
- 1072US7464242B2Method of load/store dependencies detection with dynamically changing address lengthIBM·Filed 2005·Granted Dec 9, 2008·6 cites·14 claims
- 1170US10649778B1Performance optimized congruence class matching for multiple concurrent radix translationsIBM·Filed 2018·Granted May 12, 2020·1 cites·20 claims
- 1264US11409663B2Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizesIBM·Filed 2020·Granted Aug 9, 2022·0 cites·20 claims
- 1364US7376816B2Method and systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2004·Granted May 20, 2008·8 cites·7 claims
- 1463US7769985B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2008·Granted Aug 3, 2010·2 cites·9 claims
- 1563US7730290B2Systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2008·Granted Jun 1, 2010·2 cites·13 claims
- 1663US5787478AMethod and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchyIBM·Filed 1997·Granted Jul 28, 1998·43 cites·18 claims
- 1762US11157415B2Operation of a multi-slice processor implementing a unified page walk cacheIBM·Filed 2019·Granted Oct 26, 2021·0 cites·17 claims
- 1862US7302530B2Method of updating cache state information where stores only read the cache state information upon entering the queueIBM·Filed 2004·Granted Nov 27, 2007·8 cites·26 claims
- 1959US10824494B2Operation of a multi-slice processor implementing exception handling in a nested translation environmentIBM·Filed 2018·Granted Nov 3, 2020·0 cites·20 claims
- 2059US5694573AShared L2 support for inclusion property in split L1 data and instruction cachesIBM·Filed 1996·Granted Dec 2, 1997·37 cites·2 claims
- 2156US5953351AMethod and apparatus for indicating uncorrectable data errorsIBM·Filed 1995·Granted Sep 14, 1999·35 cites·21 claims
- 2254US10042691B2Operation of a multi-slice processor implementing exception handling in a nested translation environmentIBM·Filed 2016·Granted Aug 7, 2018·0 cites·20 claims
- 2352US10534715B2Operation of a multi-slice processor implementing a unified page walk cacheIBM·Filed 2016·Granted Jan 14, 2020·0 cites·15 claims
- 2451US6202128B1Method and system for pre-fetch cache interrogation using snoop portIBM·Filed 1998·Granted Mar 13, 2001·24 cites·10 claims
- 2549US6240487B1Integrated cache buffersIBM·Filed 1998·Granted May 29, 2001·22 cites·16 claims
- 2648US6446170B1Efficient store machine in cache based microprocessorIBM·Filed 1999·Granted Sep 3, 2002·20 cites·17 claims
- 2747US7363468B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2004·Granted Apr 22, 2008·1 cites·5 claims
- 2842US5692151AHigh performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory addressIBM·Filed 1994·Granted Nov 25, 1997·13 cites·2 claims
- 2931US6298417B1Pipelined cache memory deallocation and storebackIBM·Filed 1998·Granted Oct 2, 2001·3 cites·16 claims
- 3030US6604173B1System for controlling access to external cache memories of differing sizeIBM·Filed 1995·Granted Aug 5, 2003·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →