Inventor · disambiguated record
Dyer A. Matlock
Also filed as: MATLOCK DYER A
11 granted patents·443 citations·filing 1985–1993
92Inventor score
Files withHARRIS CORP11
Top patents by PatentIndex Score
11 records- 0190US5071792AProcess for forming extremely thin integrated circuit diceHARRIS CORP·Filed 1990·Granted Dec 10, 1991·177 cites·28 claims
- 0281US4624749AElectrodeposition of submicrometer metallic interconnect for integrated circuitsHARRIS CORP·Filed 1985·Granted Nov 25, 1986·63 cites·20 claims
- 0380US5185292AProcess for forming extremely thin edge-connectable integrated circuit structureHARRIS CORP·Filed 1991·Granted Feb 9, 1993·81 cites·30 claims
- 0460US5247199AProcess for forming twin well CMOS integrated circuitsHARRIS CORP·Filed 1992·Granted Sep 21, 1993·26 cites·22 claims
- 0560US4829359ACMOS device having reduced spacing between N and P channelHARRIS CORP·Filed 1987·Granted May 9, 1989·19 cites·17 claims
- 0658US5429958AProcess for forming twin well CMOS integrated circuitsHARRIS CORP·Filed 1993·Granted Jul 4, 1995·24 cites·24 claims
- 0746US4908683ATechnique for elimination of polysilicon stringers in direct moat field oxide structureHARRIS CORP·Filed 1987·Granted Mar 13, 1990·11 cites·2 claims
- 0844US4814285AMethod for forming planarized interconnect level using selective deposition and ion implantationHARRIS CORP·Filed 1987·Granted Mar 21, 1989·13 cites·13 claims
- 0941US4716071AMethod of ensuring adhesion of chemically vapor deposited oxide to gold integrated circuit interconnect linesHARRIS CORP·Filed 1985·Granted Dec 29, 1987·11 cites·9 claims
- 1040US4713260AMethod of ensuring adhesion of chemically vapor deposited oxide to gold integrated circuit interconnect linesHARRIS CORP·Filed 1987·Granted Dec 15, 1987·10 cites·13 claims
- 1140US4702000ATechnique for elimination of polysilicon stringers in direct moat field oxide structureHARRIS CORP·Filed 1986·Granted Oct 27, 1987·8 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →