Inventor · disambiguated record
Dze-Chaung Wang
Also filed as: WANG DZE-CHAUNG
4 granted patents·113 citations·filing 1997–1998
79Inventor score
Technology areasG06F
Top patents by PatentIndex Score
4 records- 0165US5941980AApparatus and method for parallel decoding of variable-length instructions in a superscalar pipelined data processing systemIND TECH RES INST·Filed 1997·Granted Aug 24, 1999·56 cites·22 claims
- 0244US6382846B1Intermediate instruction execution processor which resolves symbolic references without modifying intermediate instruction codeINDUSTIAL TECHNOLOGY RES INST·Filed 1998·Granted May 7, 2002·24 cites·26 claims
- 0343US5819308AMethod for buffering and issuing instructions for use in high-performance superscalar microprocessorsIND TECH RES INST·Filed 1997·Granted Oct 6, 1998·18 cites·8 claims
- 0440US5974531AMethods and systems of stack renaming for superscalar stack-based data processorsIND TECH RES INST·Filed 1998·Granted Oct 26, 1999·15 cites·95 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →