Inventor · disambiguated record
Edward T. Cavanagh
Also filed as: CAVANAGH EDWARD T · CAVANAGH JR EDWARD T
14 granted patents·2 pending applications·284 citations·filing 1993–2019
93Inventor score
Top patents by PatentIndex Score
16 records- 0191US9824208B2Cloud-based active password managerCAVANAGH EDWARD T·Filed 2015·Granted Nov 21, 2017·16 cites·20 claims
- 0290US7774638B1Uncorrectable data error containment systems and methodsUNISYS CORP·Filed 2007·Granted Aug 10, 2010·31 cites·25 claims
- 0388US10638298B1Public event detection platformUNISYS CORP·Filed 2019·Granted Apr 28, 2020·13 cites·20 claims
- 0487US10750346B1Emergency incident detection platformUNISYS CORP·Filed 2019·Granted Aug 18, 2020·8 cites·18 claims
- 0584US9384060B2Dynamic allocation and assignment of virtual functions within fabricHUNTER JAMES R·Filed 2014·Granted Jul 5, 2016·11 cites·24 claims
- 0682US9652606B2Cloud-based active password managerCAVANAGH EDWARD T·Filed 2015·Granted May 16, 2017·6 cites·18 claims
- 0773US5463762AI/O subsystem with header and error detection code generation and checkingUNISYS CORP·Filed 1993·Granted Oct 31, 1995·67 cites·20 claims
- 0869US9804877B2Reset of single root PCI manager and physical functions within a fabricHUNTER JAMES R·Filed 2014·Granted Oct 31, 2017·3 cites·15 claims
- 0969US5832310ASerial I/O channel having dependent and synchronous sources of control data and user defined dataUNISYS CORP·Filed 1997·Granted Nov 3, 1998·63 cites·10 claims
- 1065US7506193B1Systems and methods for overcoming part to part skew in a substrate-mounted circuitUNISYS CORP·Filed 2005·Granted Mar 17, 2009·6 cites·14 claims
- 1164US8984193B1Line speed sequential transaction packet processingCAVANAGH EDWARD T·Filed 2007·Granted Mar 17, 2015·3 cites·26 claims
- 1263US7650443B1Methods and apparatus for allocating access to a host device bufferUNISYS CORP·Filed 2004·Granted Jan 19, 2010·10 cites·7 claims
- 1362US5553302ASerial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined dataUNISYS CORP·Filed 1993·Granted Sep 3, 1996·46 cites·19 claims
- 1457US9026865B2Software handling of hardware error handling in hypervisor-based systemsENTEZARI MEHDI·Filed 2012·Granted May 5, 2015·1 cites·18 claims
- 1543US2016077847A1Synchronization of physical functions and virtual functions within a fabricHUNTER JAMES R·Filed 2014·Application pending·0 cites
- 1634US2011246686A1Apparatus and system having pci root port and direct memory access device functionalityCAVANAGH JR EDWARD T·Filed 2010·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Edward T. Cavanagh files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →