Inventor · disambiguated record
Edmond Y. Cheung
Also filed as: CHEUNG EDMOND · CHEUNG EDMOND Y
12 granted patents·670 citations·filing 1992–2003
94Inventor score
Top patents by PatentIndex Score
12 records- 0193US6870397B1Input/output circuit with user programmable functionsXILINX INC·Filed 2003·Granted Mar 22, 2005·56 cites·2 claims
- 0293US5631577ASynchronous dual port RAMXILINX INC·Filed 1996·Granted May 20, 1997·88 cites·10 claims
- 0393US5566123ASynchronous dual port ramXILINX INC·Filed 1995·Granted Oct 15, 1996·90 cites·17 claims
- 0488US5267187ALogic structure and circuit for fast carryXILINX INC·Filed 1992·Granted Nov 30, 1993·145 cites·37 claims
- 0587US6459646B1Bank-based configuration and reconfiguration for programmable logic in a system on a chipTRISCEND CORP·Filed 2000·Granted Oct 1, 2002·54 cites·18 claims
- 0684US5523963ALogic structure and circuit for fast carryXILINX INC·Filed 1995·Granted Jun 4, 1996·106 cites·17 claims
- 0779US5405080AToy track coupling mechanismMARCHON INC·Filed 1992·Granted Apr 11, 1995·52 cites·6 claims
- 0872US6624656B1Input/output circuit with user programmable functionsTRISCEND CORP·Filed 1999·Granted Sep 23, 2003·22 cites·4 claims
- 0955US5295090ALogic structure and circuit for fast carryXILINX INC·Filed 1993·Granted Mar 15, 1994·31 cites·1 claims
- 1052US6181158B1Configuration logic to eliminate signal contention during reconfigurationXILINX INC·Filed 1998·Granted Jan 30, 2001·11 cites·5 claims
- 1150US5592105AConfiguration logic to eliminate signal contention during reconfigurationXILINX INC·Filed 1995·Granted Jan 7, 1997·9 cites·7 claims
- 1236US5770951AConfiguration logic to eliminate signal contention during reconfigurationXILINX INC·Filed 1997·Granted Jun 23, 1998·6 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →