Inventor · disambiguated record
Edward A. Mcdonald
Also filed as: MCDONALD EDWARD A
22 granted patents·2,141 citations·filing 1991–2002
97Inventor score
Top patents by PatentIndex Score
22 records- 0195US5676697ATwo-piece, bifurcated intraluminal graft for repair of aneurysmCARDIOVASCULAR DYNAMICS INC·Filed 1996·Granted Oct 14, 1997·768 cites·28 claims
- 0290US5728150AExpandable microporous prosthesisCARDIOVASCULAR DYNAMICS INC·Filed 1996·Granted Mar 17, 1998·367 cites·26 claims
- 0384US6754787B2System and method for terminating lock-step sequences in a multiprocessor systemINTEL CORP·Filed 2002·Granted Jun 22, 2004·34 cites·20 claims
- 0482US6090136ASelf expandable tubular supportRADIANCE MEDICAL SYSTEMS INC·Filed 1997·Granted Jul 18, 2000·225 cites·23 claims
- 0578US6292860B1Method for preventing deadlock by suspending operation of processors, bridges, and devicesNCR CORP·Filed 1997·Granted Sep 18, 2001·89 cites·13 claims
- 0676US6120535AMicroporous tubular prosthesisRADIANCE MEDICAL SYSTEMS INC·Filed 1997·Granted Sep 19, 2000·164 cites·12 claims
- 0775US5359715AArchitectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfacesNCR CO·Filed 1991·Granted Oct 25, 1994·71 cites·14 claims
- 0867US6128677ASystem and method for improved transfer of data between multiple processors and I/O bridgesINTEL CORP·Filed 1997·Granted Oct 3, 2000·48 cites·20 claims
- 0962US6047316AMultiprocessor computing apparatus having spin lock fairnessINTEL CORP·Filed 1997·Granted Apr 4, 2000·41 cites·17 claims
- 1058US5269005AMethod and apparatus for transferring data within a computer systemNCR CO·Filed 1991·Granted Dec 7, 1993·32 cites·16 claims
- 1157US6058475ABooting method for multi-processor computerNCR CORP·Filed 1997·Granted May 2, 2000·35 cites·3 claims
- 1257US6012127AMultiprocessor computing apparatus with optional coherency directoryINTEL CORP·Filed 1997·Granted Jan 4, 2000·33 cites·16 claims
- 1357US5418914ARetry scheme for controlling transactions between two bussesNCR CORP·Filed 1993·Granted May 23, 1995·33 cites·4 claims
- 1455US5765195AMethod for distributing interprocessor interrupt requests via cache memory coherency mechanismsNCR CORP·Filed 1995·Granted Jun 9, 1998·30 cites·7 claims
- 1554US5919268ASystem for determining the average latency of pending pipelined or split transaction requests through using two counters and logic dividerNCR CORP·Filed 1997·Granted Jul 6, 1999·28 cites·7 claims
- 1653US6026472AMethod and apparatus for determining memory page access information in a non-uniform memory access computer systemINTEL CORP·Filed 1997·Granted Feb 15, 2000·29 cites·8 claims
- 1751US6560682B1System and method for terminating lock-step sequences in a multiprocessor systemINTEL CORP·Filed 1997·Granted May 6, 2003·21 cites·19 claims
- 1849US5758065ASystem and method of establishing error precedence in a computer systemNCR CORP·Filed 1995·Granted May 26, 1998·24 cites·3 claims
- 1947US6073216ASystem and method for reliable system shutdown after coherency corruptionINTEL CORP·Filed 1997·Granted Jun 6, 2000·20 cites·20 claims
- 2042US6098113AApparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system busNCR CORP·Filed 1995·Granted Aug 1, 2000·17 cites·15 claims
- 2142US5327540AMethod and apparatus for decoding bus master arbitration levels to optimize memory transfersNCR CO·Filed 1993·Granted Jul 5, 1994·13 cites·16 claims
- 2240US5701422AMethod for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction busesNCR CORP·Filed 1995·Granted Dec 23, 1997·19 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →