Inventor · disambiguated record
Edward Colles Nevill
Also filed as: NEVILL EDWARD COLLES
13 granted patents·2 pending applications·324 citations·filing 1995–2004
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0185US6910206B1Data processing with native and interpreted program instruction wordsADVANCED RISC MACH LTD·Filed 2000·Granted Jun 21, 2005·47 cites·19 claims
- 0283US7134119B2Intercalling between native and non-native instruction setsADVANCED RISC MACH LTD·Filed 2001·Granted Nov 7, 2006·32 cites·25 claims
- 0380US7003652B2Restarting translated instructionsADVANCED RISC MACH LTD·Filed 2001·Granted Feb 21, 2006·30 cites·17 claims
- 0479US6965984B2Data processing using multiple instruction setsADVANCED RISC MACH LTD·Filed 2002·Granted Nov 15, 2005·28 cites·48 claims
- 0579US6021265AInteroperability with multiple instruction setsADVANCED RISC MACH LTD·Filed 1997·Granted Feb 1, 2000·70 cites·14 claims
- 0678US7000094B2Storing stack operands in registersADVANCED RISC MACH LTD·Filed 2001·Granted Feb 14, 2006·27 cites·15 claims
- 0774US6904517B2Data processing apparatus and method for saving return stateADVANCED RISC MACH LTD·Filed 2001·Granted Jun 7, 2005·20 cites·18 claims
- 0871US5758115AInteroperability with multiple instruction setsADVANCED RISC MACH LTD·Filed 1995·Granted May 26, 1998·50 cites·12 claims
- 0962USRE43248EInteroperability with multiple instruction setsNEVILL EDWARD COLLES·Filed 2002·Granted Mar 13, 2012·8 cites·69 claims
- 1055US7788472B2Instruction encoding within a data processing apparatus having multiple instruction setsADVANCED RISC MACH LTD·Filed 2004·Granted Aug 31, 2010·4 cites·33 claims
- 1155US7162611B2Unhandled operation handling in multiple instruction set systemsADVANCED RISC MACH LTD·Filed 2002·Granted Jan 9, 2007·4 cites·60 claims
- 1251US7076771B2Instruction interpretation within a data processing systemADVANCED RISC MACH LTD·Filed 2000·Granted Jul 11, 2006·2 cites·14 claims
- 1348US8176286B2Memory recycling in computer systemsNEVILL EDWARD COLLES·Filed 2004·Granted May 8, 2012·2 cites·30 claims
- 1443US2002069402A1Scheduling control within a system having mixed hardware and software based instruction executionFiled 2000·Application pending·0 cites
- 1541US2002083302A1Hardware instruction translation within a processor pipelineFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →