Inventor · disambiguated record
Elise Baylac
Also filed as: BAYLAC ELISE
2 granted patents·2 pending applications·1 citations·filing 2014–2016
30Inventor score
Top patents by PatentIndex Score
4 records- 0165US10263110B2Method of forming strained MOS transistorsST MICROELECTRONICS CROLLES 2 SAS·Filed 2016·Granted Apr 16, 2019·1 cites·10 claims
- 0247US2015097241A1Method for relaxing the transverse mechanical stresses within the active region of a mos transistor, and corresponding integrated circuitST MICROELECTRONICS CROLLES 2·Filed 2014·Application pending·0 cites
- 0344US9543214B2Method of forming stressed semiconductor layerST MICROELECTRONICS SA·Filed 2014·Granted Jan 10, 2017·0 cites·22 claims
- 0441US2016099183A1Method for relaxing the transverse mechanical stresses within the active region of a mos transistor, and corresponding integrated circuitST MICROELECTRONICS CROLLES 2·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →