Inventor · disambiguated record
Elizabeth A. Mcglone
Also filed as: MCGLONE ELIZABETH · MCGLONE ELIZABETH A
45 granted patents·7 pending applications·217 citations·filing 2004–2018
98Inventor score
Top patents by PatentIndex Score
52 records- 0196US10037211B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2016·Granted Jul 31, 2018·15 cites·17 claims
- 0291US10042647B2Managing a divided load reorder queueIBM·Filed 2016·Granted Aug 7, 2018·6 cites·20 claims
- 0391US10042770B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Aug 7, 2018·6 cites·7 claims
- 0491US10037229B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Jul 31, 2018·6 cites·13 claims
- 0591US9983875B2Operation of a multi-slice processor preventing early dependent instruction wakeupIBM·Filed 2016·Granted May 29, 2018·9 cites·17 claims
- 0691US9043526B2Versatile lane configuration using a PCIe PIe-8 interfaceFREKING RONALD E·Filed 2012·Granted May 26, 2015·16 cites·12 claims
- 0790US7328315B2System and method for managing mirrored memory transactions and error recoveryIBM·Filed 2005·Granted Feb 5, 2008·21 cites·9 claims
- 0889US8949499B2Using a PCI standard hot plug controller to modify the hierarchy of a distributed switchFREKING RONALD E·Filed 2012·Granted Feb 3, 2015·12 cites·12 claims
- 0989US7984357B2Implementing minimized latency and maximized reliability when data traverses multiple busesIBM·Filed 2007·Granted Jul 19, 2011·21 cites·12 claims
- 1088US7882323B2Scheduling of background scrub commands to reduce high workload memory request latencyIBM·Filed 2007·Granted Feb 1, 2011·19 cites·9 claims
- 1182US9292460B2Versatile lane configuration using a PCIe PIE-8 interfaceIBM·Filed 2013·Granted Mar 22, 2016·6 cites·7 claims
- 1279US9684618B2Peripheral component interconnect express (PCIe) ping in a switch-based environmentIBM·Filed 2014·Granted Jun 20, 2017·4 cites·7 claims
- 1379US7882314B2Efficient scheduling of background scrub commandsIBM·Filed 2007·Granted Feb 1, 2011·9 cites·12 claims
- 1475US9292462B2Broadcast for a distributed switch networkIBM·Filed 2013·Granted Mar 22, 2016·4 cites·19 claims
- 1575US9087162B2Using a PCI standard hot plug controller to modify the hierarchy of a distributed switchIBM·Filed 2013·Granted Jul 21, 2015·3 cites·8 claims
- 1674US10564978B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2018·Granted Feb 18, 2020·1 cites·14 claims
- 1772US8572455B2Systems and methods to respond to error detectionBLACKMON H LEE·Filed 2009·Granted Oct 29, 2013·6 cites·20 claims
- 1870US9563591B2Peripheral component interconnect express (PCIe) ping in a switch-based environmentIBM·Filed 2014·Granted Feb 7, 2017·2 cites·14 claims
- 1970US8898359B2Bandwidth limiting on generated PCIe packets from debug sourceIBM·Filed 2013·Granted Nov 25, 2014·2 cites·7 claims
- 2070US8266331B2Transmitting retry request associated with non-posted command via response credit channelFREKING RONALD E·Filed 2010·Granted Sep 11, 2012·4 cites·20 claims
- 2170US8103930B2Apparatus for implementing processor bus speculative data completionBARRETT WAYNE MELVIN·Filed 2008·Granted Jan 24, 2012·4 cites·5 claims
- 2270US7472236B2Managing mirrored memory transactions and error recoveryIBM·Filed 2007·Granted Dec 30, 2008·4 cites·18 claims
- 2369US8706938B2Bandwidth limiting on generated PCIE packets from debug sourceFREKING RONALD E·Filed 2012·Granted Apr 22, 2014·2 cites·14 claims
- 2469US8397100B2Managing memory refreshesBLACKMON H LEE·Filed 2010·Granted Mar 12, 2013·3 cites·20 claims
- 2569US7761669B2Memory controller granular read queue dynamic optimization of command selectionIBM·Filed 2007·Granted Jul 20, 2010·5 cites·7 claims
- 2668US7426672B2Method for implementing processor bus speculative data completionIBM·Filed 2005·Granted Sep 16, 2008·3 cites·9 claims
- 2767US8132048B2Systems and methods to efficiently schedule commands at a memory controllerBLACKMON H LEE·Filed 2009·Granted Mar 6, 2012·4 cites·20 claims
- 2864US7516270B2Memory controller and method for scrubbing memory without using explicit atomic operationsIBM·Filed 2007·Granted Apr 7, 2009·2 cites·6 claims
- 2963US10268518B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 23, 2019·0 cites·13 claims
- 3063US10255107B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 9, 2019·0 cites·7 claims
- 3163US8352786B2Compressed replay bufferIBM·Filed 2010·Granted Jan 8, 2013·1 cites·12 claims
- 3263US8127087B2Memory controller for improved read port selection in a memory mirrored systemBLACKMON HERMAN L·Filed 2009·Granted Feb 28, 2012·4 cites·19 claims
- 3362US8539309B2System and method for responding to error detectionBLACKMON H LEE·Filed 2009·Granted Sep 17, 2013·2 cites·21 claims
- 3462US8001354B2Implementing dynamic physical memory reallocationIBM·Filed 2007·Granted Aug 16, 2011·2 cites·14 claims
- 3562US7793034B2Memory controller and method for multi-path address translation in non-uniform memory configurationsIBM·Filed 2007·Granted Sep 7, 2010·2 cites·20 claims
- 3660US8793539B2External settings that reconfigure the error handling behavior of a distributed PCIe switchFREKING RONALD E·Filed 2012·Granted Jul 29, 2014·1 cites·16 claims
- 3759US8055813B2Flexible and efficient configuration of multiple common interfacesIBM·Filed 2008·Granted Nov 8, 2011·1 cites·20 claims
- 3856US8205138B2Memory controller for reducing time to initialize main memoryBLACKMON HERMAN L·Filed 2008·Granted Jun 19, 2012·1 cites·11 claims
- 3956US2018260230A1Managing a divided load reorder queueIBM·Filed 2018·Application pending·0 cites
- 4053US7257686B2Memory controller and method for scrubbing memory without using explicit atomic operationsIBM·Filed 2004·Granted Aug 14, 2007·2 cites·8 claims
- 4152US7949836B2Memory controller and method for copying mirrored memory that allows processor accesses to memory during a mirror copy operationIBM·Filed 2004·Granted May 24, 2011·2 cites·9 claims
- 4250US9122604B2External settings that reconfigure the error handling behavior of a distributed PCIe switchIBM·Filed 2013·Granted Sep 1, 2015·0 cites·8 claims
- 4349US10318419B2Flush avoidance in a load store unitIBM·Filed 2016·Granted Jun 11, 2019·0 cites·20 claims
- 4447US9916245B2Accessing partial cachelines in a data cacheIBM·Filed 2016·Granted Mar 13, 2018·0 cites·17 claims
- 4547US2009216959A1Multi Port Memory Controller QueuingALLISON BRIAN DAVID·Filed 2008·Application pending·0 cites
- 4647US2009307523A1System Performance Through Invalidation of Speculative Memory Scrub CommandsALLISON BRIAN D·Filed 2008·Application pending·0 cites
- 4747US2009216960A1Multi Port Memory Controller QueuingALLISON BRIAN DAVID·Filed 2008·Application pending·0 cites
- 4845US10761854B2Preventing hazard flushes in an instruction sequencing unit of a multi-slice processorIBM·Filed 2016·Granted Sep 1, 2020·0 cites·17 claims
- 4945US10346174B2Operation of a multi-slice processor with dynamic canceling of partial loadsIBM·Filed 2016·Granted Jul 9, 2019·0 cites·20 claims
- 5044US2009019238A1Memory Controller Read Queue Dynamic Optimization of Command SelectionALLISON BRIAN DAVID·Filed 2007·Application pending·0 cites
Showing the top 50 of 52 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →