Inventor · disambiguated record
Ely Tsern
Also filed as: TSERN ELY · TSERN ELY K
244 granted patents·39 pending applications·7,363 citations·filing 1997–2025
99Inventor score
Top patents by PatentIndex Score
283 records- 0199US10381067B2Memory system topologies including a buffer device and an integrated circuit memory deviceRAMBUS INC·Filed 2017·Granted Aug 13, 2019·23 cites·19 claims
- 0299US7660183B2Low power memory deviceRAMBUS INC·Filed 2005·Granted Feb 9, 2010·109 cites·28 claims
- 0399US7464225B2Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topologyRAMBUS INC·Filed 2005·Granted Dec 9, 2008·156 cites·36 claims
- 0499US7003618B2System featuring memory modules that include an integrated circuit buffer devicesRAMBUS INC·Filed 2005·Granted Feb 21, 2006·103 cites·24 claims
- 0599US7000062B2System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devicesRAMBUS INC·Filed 2005·Granted Feb 14, 2006·185 cites·28 claims
- 0699US6701446B2Power control system for synchronous memory deviceRAMBUS INC·Filed 2001·Granted Mar 2, 2004·184 cites·40 claims
- 0799US6675272B2Method and apparatus for coordinating memory operations among diversely-located memory componentsRAMBUS INC·Filed 2001·Granted Jan 6, 2004·224 cites·28 claims
- 0899US6502161B1Memory system including a point-to-point linked memory subsystemRAMBUS INC·Filed 2000·Granted Dec 31, 2002·596 cites·49 claims
- 0998US11727982B2Memory system topologies including a memory die stackRAMBUS INC·Filed 2022·Granted Aug 15, 2023·3 cites·20 claims
- 1098US11043258B2Memory system topologies including a memory die stackRAMBUS INC·Filed 2020·Granted Jun 22, 2021·5 cites·20 claims
- 1198US9390782B2Memory with refresh logic to accommodate low-retention storage rowsRAMBUS INC·Filed 2014·Granted Jul 12, 2016·59 cites·20 claims
- 1298US8359445B2Method and apparatus for signaling between devices of a memory systemRAMBUS INC·Filed 2009·Granted Jan 22, 2013·62 cites·35 claims
- 1398US7831882B2Memory system with error detection and retry modes of operationRAMBUS INC·Filed 2005·Granted Nov 9, 2010·59 cites·13 claims
- 1498US7581121B2System for a memory device having a power down mode and methodRAMBUS INC·Filed 2005·Granted Aug 25, 2009·76 cites·21 claims
- 1598US7565479B2Memory with refresh cycle donation to accommodate low-retention-storage rowsRAMBUS INC·Filed 2005·Granted Jul 21, 2009·103 cites·32 claims
- 1698US7562271B2Memory system topologies including a buffer device and an integrated circuit memory deviceRAMBUS INC·Filed 2007·Granted Jul 14, 2009·68 cites·10 claims
- 1798US7444577B2Memory device testing to support address-differentiated refresh ratesRAMBUS INC·Filed 2005·Granted Oct 28, 2008·120 cites·16 claims
- 1898US7210016B2Method, system and memory controller utilizing adjustable write data delay settingsRAMBUS INC·Filed 2005·Granted Apr 24, 2007·47 cites·24 claims
- 1998US7209397B2Memory device with clock multiplier circuitRAMBUS INC·Filed 2005·Granted Apr 24, 2007·56 cites·22 claims
- 2098US7177998B2Method, system and memory controller utilizing adjustable read data delay settingsRAMBUS INC·Filed 2006·Granted Feb 13, 2007·50 cites·24 claims
- 2198US7010642B2System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devicesRAMBUS INC·Filed 2004·Granted Mar 7, 2006·119 cites·44 claims
- 2298US6920540B2Timing calibration apparatus and method for a memory device signaling systemRAMBUS INC·Filed 2002·Granted Jul 19, 2005·128 cites·67 claims
- 2398US6839266B1Memory module with offset data lines and bit line swizzle configurationRAMBUS INC·Filed 2002·Granted Jan 4, 2005·189 cites·12 claims
- 2498US6343042B1DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2000·Granted Jan 29, 2002·99 cites·9 claims
- 2598US6154821AMethod and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domainRAMBUS INC·Filed 1998·Granted Nov 28, 2000·237 cites·24 claims
- 2697US11328764B2Memory system topologies including a memory die stackRAMBUS INC·Filed 2021·Granted May 10, 2022·3 cites·20 claims
- 2797US8756368B2Memory controller with refresh logic to accommodate low-retention storage rows in a memory deviceBEST SCOTT C·Filed 2009·Granted Jun 17, 2014·55 cites·21 claims
- 2897US8717837B2Memory moduleRAMBUS INC·Filed 2013·Granted May 6, 2014·20 cites·20 claims
- 2997US8625371B2Memory component with terminated and unterminated signaling inputsRAMBUS INC·Filed 2013·Granted Jan 7, 2014·20 cites·20 claims
- 3097US8537601B2Memory controller with selective data transmission delayWARE FREDERICK A·Filed 2012·Granted Sep 17, 2013·20 cites·18 claims
- 3197US8108607B2Memory system topologies including a buffer device and an integrated circuit memory deviceSHAEFFER IAN·Filed 2010·Granted Jan 31, 2012·25 cites·24 claims
- 3297US7577789B2Upgradable memory system with reconfigurable interconnectRAMBUS INC·Filed 2006·Granted Aug 18, 2009·50 cites·28 claims
- 3397US7225292B2Memory module with termination componentRAMBUS INC·Filed 2005·Granted May 29, 2007·42 cites·22 claims
- 3497US7200055B2Memory module with termination componentRAMBUS INC·Filed 2005·Granted Apr 3, 2007·42 cites·24 claims
- 3597US6266292B1DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2000·Granted Jul 24, 2001·82 cites·46 claims
- 3697US6075744ADram core refresh with reduced spike currentRAMBUS INC·Filed 1998·Granted Jun 13, 2000·110 cites·11 claims
- 3796US11755508B2High-performance, high-capacity memory systems and modulesRAMBUS INC·Filed 2021·Granted Sep 12, 2023·3 cites·12 claims
- 3896US11556433B2High performance persistent memoryRAMBUS INC·Filed 2021·Granted Jan 17, 2023·3 cites·20 claims
- 3996US10236051B2Memory controllerRAMBUS INC·Filed 2017·Granted Mar 19, 2019·7 cites·20 claims
- 4096US9563597B2High capacity memory systems with inter-rank skew toleranceRAMBUS INC·Filed 2012·Granted Feb 7, 2017·22 cites·18 claims
- 4196US8462566B2Memory module with termination componentWARE FREDERICK A·Filed 2008·Granted Jun 11, 2013·24 cites·34 claims
- 4296US8059476B2Control component for controlling a delay interval within a memory componentWARE FREDERICK A·Filed 2010·Granted Nov 15, 2011·15 cites·21 claims
- 4396US7734866B2Memory with address-differentiated refresh rate to accommodate low-retention storage rowsRAMBUS INC·Filed 2005·Granted Jun 8, 2010·54 cites·23 claims
- 4496US7003639B2Memory controller with power management logicRAMBUS INC·Filed 2004·Granted Feb 21, 2006·126 cites·21 claims
- 4596US6842864B1Method and apparatus for configuring access times of memory devicesRAMBUS INC·Filed 2000·Granted Jan 11, 2005·99 cites·32 claims
- 4696US6765800B2Multiple channel modules and bus systems using sameRAMBUS INC·Filed 2001·Granted Jul 20, 2004·73 cites·14 claims
- 4796US6597616B2DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2002·Granted Jul 22, 2003·73 cites·32 claims
- 4896US6263448B1Power control system for synchronous memory deviceRAMBUS INC·Filed 1998·Granted Jul 17, 2001·186 cites·35 claims
- 4995US9472262B2Memory controllerRAMBUS INC·Filed 2016·Granted Oct 18, 2016·6 cites·20 claims
- 5095US9311976B2Memory moduleRAMBUS INC·Filed 2014·Granted Apr 12, 2016·11 cites·20 claims
Showing the top 50 of 283 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →