Inventor · disambiguated record
Emmanuel Petitprez
Also filed as: PETITPREZ EMMANUEL
7 granted patents·1 pending application·10 citations·filing 2007–2021
75Inventor score
Files withST MICROELECTRONICS CROLLES 2 SAS2ST MICROELECTRONICS ROUSSET2Aledia1BRAECKELMANN GREG1IBM1
Top patents by PatentIndex Score
8 records- 0177US8848417B2Integrated circuit with a self-programmed identification keyPETITPREZ EMMANUEL·Filed 2012·Granted Sep 30, 2014·8 cites·20 claims
- 0274US9590064B2Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuitST MICROELECTRONICS CROLLES 2 SAS·Filed 2015·Granted Mar 7, 2017·2 cites·17 claims
- 0366US11818901B2Integrated circuit including bipolar transistorsST MICROELECTRONICS ROUSSET·Filed 2021·Granted Nov 14, 2023·0 cites·19 claims
- 0454US11152430B2Integrated circuit including bipolar transistorsST MICROELECTRONICS ROUSSET·Filed 2019·Granted Oct 19, 2021·0 cites·20 claims
- 0551US2023307486A1Method for manufacturing an optoelectronic deviceAledia·Filed 2021·Application pending·0 cites
- 0646US9922871B2Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuitST MICROELECTRONICS CROLLES 2 SAS·Filed 2017·Granted Mar 20, 2018·0 cites·16 claims
- 0742US8202798B2Improvements for reducing electromigration effect in an integrated circuitBRAECKELMANN GREG·Filed 2007·Granted Jun 19, 2012·0 cites·20 claims
- 0839US9608080B2Method and structure to reduce parasitic capacitance in raised source/drain silicon-on-insulator devicesIBM·Filed 2015·Granted Mar 28, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →