Inventor · disambiguated record
Eric Delano
Also filed as: DELANO ERIC · DELANO ERIC R · DELANO ERIC RICHARD
41 granted patents·7 pending applications·1,056 citations·filing 1991–2018
98Inventor score
Top patents by PatentIndex Score
48 records- 0193US7398374B2Multi-cluster processor for processing instructions of one or more instruction threadsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jul 8, 2008·95 cites·11 claims
- 0291US8171121B2Method, system, and apparatus for dynamic reconfiguration of resourcesAYYAR MANI·Filed 2008·Granted May 1, 2012·22 cites·3 claims
- 0390US6427188B1Method and system for early tag accesses for lower-level caches in parallel with first-level cacheHEWLETT PACKARD CO·Filed 2000·Granted Jul 30, 2002·67 cites·20 claims
- 0486US7237144B2Off-chip lockstep checkingHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Jun 26, 2007·43 cites·33 claims
- 0584US9798556B2Method, system, and apparatus for dynamic reconfiguration of resourcesINTEL CORP·Filed 2015·Granted Oct 24, 2017·3 cites·12 claims
- 0684US9183144B2Power gating a portion of a cache memoryINTEL CORP·Filed 2012·Granted Nov 10, 2015·7 cites·17 claims
- 0783US7290169B2Core-level processor locksteppingHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Oct 30, 2007·39 cites·34 claims
- 0883US6941489B2Checkpointing of register fileHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 6, 2005·34 cites·20 claims
- 0983US5787494ASoftware assisted hardware TLB miss handlerHEWLETT PACKARD CO·Filed 1995·Granted Jul 28, 1998·114 cites·13 claims
- 1081US9176875B2Power gating a portion of a cache memoryINTEL CORP·Filed 2013·Granted Nov 3, 2015·5 cites·17 claims
- 1181US5603004AMethod for decreasing time penalty resulting from a cache miss in a multi-level cache systemHEWLETT PACKARD CO·Filed 1994·Granted Feb 11, 1997·102 cites·29 claims
- 1280US10725920B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 28, 2020·2 cites·26 claims
- 1380US10705960B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 7, 2020·2 cites·21 claims
- 1480US7028167B2Core parallel execution with different optimization characteristics to decrease dynamic execution pathHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 11, 2006·28 cites·20 claims
- 1580US5337415APredecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequencyHEWLETT PACKARD CO·Filed 1992·Granted Aug 9, 1994·96 cites·2 claims
- 1678US5493660ASoftware assisted hardware TLB miss handlerHEWLETT PACKARD CO·Filed 1992·Granted Feb 20, 1996·75 cites·2 claims
- 1776US7421689B2Processor-architecture for facilitating a virtual machine monitorHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 2, 2008·22 cites·12 claims
- 1876US7296181B2Lockstep error signalingHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Nov 13, 2007·22 cites·48 claims
- 1975US10725919B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 28, 2020·1 cites·22 claims
- 2074US6049851AMethod and apparatus for checking cache coherency in a computer architectureHEWLETT PACKARD CO·Filed 1994·Granted Apr 11, 2000·65 cites·10 claims
- 2172US9223738B2Method, system, and apparatus for dynamic reconfiguration of resourcesAYYAR MANI·Filed 2012·Granted Dec 29, 2015·2 cites·17 claims
- 2271US8219780B2Mitigating context switch cache miss penaltyCALLISTER JAMES R·Filed 2005·Granted Jul 10, 2012·7 cites·17 claims
- 2370US9792212B2Virtual shared cache mechanism in a processing deviceINTEL CORP·Filed 2014·Granted Oct 17, 2017·2 cites·20 claims
- 2470US8327113B2Method, system, and apparatus for dynamic reconfiguration of resourcesAYYAR MANI·Filed 2008·Granted Dec 4, 2012·3 cites·4 claims
- 2569US7734741B2Method, system, and apparatus for dynamic reconfiguration of resourcesINTEL CORP·Filed 2004·Granted Jun 8, 2010·10 cites·4 claims
- 2668US6931489B2Apparatus and methods for sharing cache among processorsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Aug 16, 2005·13 cites·19 claims
- 2766US10073779B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2012·Granted Sep 11, 2018·1 cites·21 claims
- 2864US7930539B2Computer system resource access controlHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Apr 19, 2011·9 cites·23 claims
- 2963US5404496AComputer-based system and method for debugging a computer system implementationHEWLETT PACKARD CO·Filed 1992·Granted Apr 4, 1995·49 cites·19 claims
- 3062US7370135B2Band configuration agent for link based computing systemINTEL CORP·Filed 2005·Granted May 6, 2008·2 cites·20 claims
- 3161US8799586B2Memory mirroring and migration at home agentKUMAR GANESH·Filed 2009·Granted Aug 5, 2014·3 cites·23 claims
- 3260US5396604ASystem and method for reducing the penalty associated with data cache missesHEWLETT PACKARD CO·Filed 1991·Granted Mar 7, 1995·37 cites·14 claims
- 3359US7310751B2Timeout event trigger generationHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Dec 18, 2007·6 cites·33 claims
- 3458US8327228B2Home agent data and memory managementKUMAR GANESH·Filed 2009·Granted Dec 4, 2012·2 cites·35 claims
- 3558US6820167B2Configurable crossbar and related methodsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Nov 16, 2004·5 cites·17 claims
- 3656US6895497B2Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priorityHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted May 17, 2005·5 cites·5 claims
- 3752US5471602ASystem and method of scoreboarding individual cache line segmentsHEWLETT PACKARD CO·Filed 1992·Granted Nov 28, 1995·23 cites·17 claims
- 3850US5617549ASystem and method for selecting and buffering even and odd instructions for simultaneous execution in a computerHEWLETT PACKARD CO·Filed 1994·Granted Apr 1, 1997·21 cites·19 claims
- 3946US8782347B2Controllably exiting an unknown state of a cache coherency directoryKUMAR GANESH·Filed 2009·Granted Jul 15, 2014·0 cites·12 claims
- 4046US2006031672A1Resource protection in a computer system with direct hardware resource accessSOLTIS DONALD C JR·Filed 2004·Application pending·0 cites
- 4145US7451260B2Interleave mechanism for a computing environmentHEWLETT PACKARD DEVELOPMENT CO·Filed 2006·Granted Nov 11, 2008·0 cites·20 claims
- 4244US2004225830A1Apparatus and methods for linking a processor and cacheFiled 2003·Application pending·0 cites
- 4344US2005108509A1Error detection method and system for processors that employs lockstepped concurrent threadsFiled 2003·Application pending·0 cites
- 4444US2005138478A1Error detection method and system for processors that employ alternating threadsFiled 2003·Application pending·0 cites
- 4543US2003135291A1Customized ports in a crossbar and method for transmitting data between customized ports and system agentsFiled 2002·Application pending·0 cites
- 4638US2003145171A1Simplified cache hierarchy by using multiple tags and entries into a large subdivided arrayFiled 2002·Application pending·0 cites
- 4737US2007150699A1Firm partitioning in a system with a point-to-point interconnectSCHOINAS IOANNIS T·Filed 2005·Application pending·0 cites
- 4835US5526500ASystem for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructionsHEWLETT PACKARD CO·Filed 1995·Granted Jun 11, 1996·12 cites·29 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →