Inventor · disambiguated record
Ertugrul Demircan
Also filed as: DEMIRCAN ERTUGRUL
13 granted patents·6 pending applications·112 citations·filing 2003–2024
90Inventor score
Top patents by PatentIndex Score
19 records- 0190US6765778B1Integrated vertical stack capacitorFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jul 20, 2004·63 cites·22 claims
- 0286US8713498B2Method and system for physical verification using network segment currentSHROFF MEHUL D·Filed 2011·Granted Apr 29, 2014·10 cites·17 claims
- 0385US8510695B1Techniques for electromigration stress determination in interconnects of an integrated circuitDEMIRCAN ERTUGRUL·Filed 2012·Granted Aug 13, 2013·10 cites·20 claims
- 0481US8793632B2Techniques for electromigration stress determination in interconnects of an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Jul 29, 2014·6 cites·20 claims
- 0579US9934349B2Method for verifying design rule checksFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Apr 3, 2018·5 cites·20 claims
- 0676US8431970B2Integrated circuits with edge-adjacent devices having reactance valuesDEMIRCAN ERTUGRUL·Filed 2010·Granted Apr 30, 2013·4 cites·16 claims
- 0772US9652577B2Integrated circuit design using pre-marked circuit element object libraryTRAVIS EDWARD O·Filed 2014·Granted May 16, 2017·3 cites·11 claims
- 0870US7386821B2Primitive cell method for front end physical designFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jun 10, 2008·5 cites·5 claims
- 0967US7820520B2Semiconductor device with capacitor and/or inductor and method of makingFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Oct 26, 2010·3 cites·15 claims
- 1063US2025385126A1Interconnect structure with relaxed via-corner slopeNXP USA INC·Filed 2024·Application pending·0 cites
- 1162US9026970B2Prioritized design for manufacturing virtualization with design rule checking filteringDANTI KENNETH J·Filed 2013·Granted May 5, 2015·3 cites·20 claims
- 1262US2025336718A1Low-k interconnect dielectric by selective implantationNXP USA INC·Filed 2024·Application pending·0 cites
- 1360US2025185360A1Latch-up prevention with well-tie extension using selective well dopingNXP BV·Filed 2023·Application pending·0 cites
- 1459US2025063768A1Integrated circuit with overlapping stressorsNXP USA INC·Filed 2023·Application pending·0 cites
- 1559US2025105171A1Integrated circuit with dielectric layer having selectively implanted stress-setting dopantsNXP USA INC·Filed 2023·Application pending·0 cites
- 1656US9219107B2Inductive element with interrupter region and method for formingDEMIRCAN ERTUGRUL·Filed 2014·Granted Dec 22, 2015·0 cites·6 claims
- 1752US8766402B2Inductive element with interrupter regionDEMIRCAN ERTUGRUL·Filed 2012·Granted Jul 1, 2014·0 cites·11 claims
- 1849US9245086B2Techniques for electromigration stress mitigation in interconnects of an integrated circuit designDEMIRCAN ERTUGRUL·Filed 2014·Granted Jan 26, 2016·0 cites·20 claims
- 1945US2015178438A1Semiconductor manufacturing using design verification with markersDEMIRCAN ERTUGRUL·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →