Inventor · disambiguated record
Erik G. Hallnor
Also filed as: HALLNOR ERIK · HALLNOR ERIK G
10 granted patents·4 pending applications·29 citations·filing 2008–2025
84Inventor score
Top patents by PatentIndex Score
14 records- 0189US9710041B2Masking a power state of a core of a processorINTEL CORP·Filed 2015·Granted Jul 18, 2017·7 cites·21 claims
- 0279US8392657B2Monitoring cache usage in a distributed shared cacheZHAO LI·Filed 2009·Granted Mar 5, 2013·10 cites·17 claims
- 0371US9954792B2Shared flow control creditsINTEL CORP·Filed 2014·Granted Apr 24, 2018·3 cites·19 claims
- 0469US10599335B2Supporting hierarchical ordering points in a microprocessor systemINTEL CORP·Filed 2018·Granted Mar 24, 2020·1 cites·17 claims
- 0565US8316184B2Domain-based cache management, including domain event based priority demotionFANG ZHEN·Filed 2008·Granted Nov 20, 2012·2 cites·20 claims
- 0662US8090967B2Power state transition initiation control of memory interconnect based on early warning signal, memory response time, and wakeup delayHALLNOR ERIK G·Filed 2008·Granted Jan 3, 2012·4 cites·19 claims
- 0759US10705961B2Scalably mechanism to implement an instruction that monitors for writes to an addressLIU YEN CHENG·Filed 2013·Granted Jul 7, 2020·1 cites·21 claims
- 0855US9336156B2Method and apparatus for cache line state update in sectored cache with line state trackerZHANG ZHONGYING·Filed 2013·Granted May 10, 2016·1 cites·24 claims
- 0947US9785223B2Power management in an uncore fabricINTEL CORP·Filed 2014·Granted Oct 10, 2017·0 cites·18 claims
- 1047US2025203125A1Dynamic cache allocation for display pixel data cachingINTEL CORP·Filed 2025·Application pending·0 cites
- 1147US2023350814A1Device, method and system to supplement a cache with a randomized victim cacheINTEL CORP·Filed 2022·Application pending·0 cites
- 1246US2016188503A1Virtual legacy wireINTEL CORP·Filed 2014·Application pending·0 cites
- 1343US10877886B2Storing cache lines in dedicated cache of an idle coreINTEL CORP·Filed 2018·Granted Dec 29, 2020·0 cites·20 claims
- 1435US2016283232A1Instruction and Logic for Speculative Request Support for PrefetchingSADE RAANAN·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →