Inventor · disambiguated record
Ervin T. Hill
Also filed as: HILL ERVIN · HILL ERVIN T · HILL III ERVIN T
9 granted patents·2 pending applications·17 citations·filing 2003–2022
83Inventor score
Top patents by PatentIndex Score
11 records- 0178US10672500B2Non-contact measurement of memory cell threshold voltageMICRON TECHNOLOGY INC·Filed 2019·Granted Jun 2, 2020·2 cites·20 claims
- 0276US10650891B2Non-contact electron beam probing techniques and related structuresMICRON TECHNOLOGY INC·Filed 2019·Granted May 12, 2020·3 cites·17 claims
- 0369US10403359B2Non-contact electron beam probing techniques and related structuresMICRON TECHNOLOGY INC·Filed 2018·Granted Sep 3, 2019·2 cites·5 claims
- 0466US7943463B2Methods of semiconductor processing involving forming doped polysilicon on undoped polysiliconMICRON TECHNOLOGY INC·Filed 2009·Granted May 17, 2011·3 cites·18 claims
- 0562US2021296582A1Dielectric barrier at non-volatile memory tile edgeINTEL CORP·Filed 2021·Application pending·0 cites
- 0661US8072022B2Apparatus and methods for improved flash cell characteristicsKALAVADE PRANAV·Filed 2008·Granted Dec 6, 2011·2 cites·20 claims
- 0759US11069855B2Dielectric barrier at non-volatile memory tile edgeINTEL CORP·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 0855US10381101B2Non-contact measurement of memory cell threshold voltageMICRON TECHNOLOGY INC·Filed 2017·Granted Aug 13, 2019·0 cites·3 claims
- 0951US2023422639A1Semiconductor structure including barrier layer between electrode layer and underlying substrateINTEL CORP·Filed 2022·Application pending·0 cites
- 1045US7153780B2Method and apparatus for self-aligned MOS patterningINTEL CORP·Filed 2004·Granted Dec 26, 2006·4 cites·27 claims
- 1140US7186614B2Method for manufacturing high density flash memory and high performance logic on a single dieINTEL CORP·Filed 2003·Granted Mar 6, 2007·1 cites·28 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →