Inventor · disambiguated record
Erich C. Schanzenbach
Also filed as: SCHANZENBACH ERICH · SCHANZENBACH ERICH C
10 granted patents·174 citations·filing 1995–2021
89Inventor score
Top patents by PatentIndex Score
10 records- 0190US6631502B2Method of analyzing integrated circuit power distribution in chips containing voltage islandsIBM·Filed 2002·Granted Oct 7, 2003·88 cites·16 claims
- 0282US6725439B1Method of automated design and checking for ESD robustnessIBM·Filed 2000·Granted Apr 20, 2004·44 cites·19 claims
- 0380US9582622B1Evaluating on-chip voltage regulationIBM·Filed 2015·Granted Feb 28, 2017·4 cites·20 claims
- 0477US7496877B2Electrostatic discharge failure avoidance through interaction between floorplanning and power routingIBM·Filed 2005·Granted Feb 24, 2009·9 cites·18 claims
- 0570US12038034B2Self-drilling, anti-burr, threaded fastenerSFS Group International AG·Filed 2021·Granted Jul 16, 2024·1 cites·17 claims
- 0667US7234124B2Method and apparatus for performing power routing on a voltage island within an integrated circuit chipIBM·Filed 2004·Granted Jun 19, 2007·12 cites·6 claims
- 0764US9607118B1Evaluating on-chip voltage regulationIBM·Filed 2016·Granted Mar 28, 2017·1 cites·1 claims
- 0854US6861753B1Method and apparatus for performing power routing on a voltage island within an integrated circuit chipIBM·Filed 2003·Granted Mar 1, 2005·5 cites·12 claims
- 0942US10467372B2Implementing automated identification of optimal sense point and sector locations in various on-chip linear voltage regulator designsIBM·Filed 2017·Granted Nov 5, 2019·0 cites·18 claims
- 1033US5631842AParallel approach to chip wiringIBM·Filed 1995·Granted May 20, 1997·10 cites·26 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →