Inventor · disambiguated record
Eugene L. Parrella
Also filed as: PARRELLA EUGENE · PARRELLA EUGENE L
7 granted patents·2 pending applications·378 citations·filing 1994–2021
89Inventor score
Top patents by PatentIndex Score
9 records- 0188US5615237ATelecommunications framer utilizing state machineTRANSWITCH CORP·Filed 1994·Granted Mar 25, 1997·91 cites·22 claims
- 0281US6246682B1Method and apparatus for managing multiple ATM cell queuesTRANSWITCH CORP·Filed 1999·Granted Jun 12, 2001·152 cites·26 claims
- 0366US6765867B2Method and apparatus for avoiding head of line blocking in an ATM (asynchronous transfer mode) deviceTRANSWITCH CORP·Filed 2002·Granted Jul 20, 2004·19 cites·39 claims
- 0463US6134653ARISC processor architecture with high performance context switching in which one context can be loaded by a co-processor while another context is being accessed by an arithmetic logic unitTRANSWITCH CORP·Filed 1998·Granted Oct 17, 2000·50 cites·20 claims
- 0560US6321331B1Real time debugger interface for embedded systemsTRANSWITCH CORP·Filed 1998·Granted Nov 20, 2001·36 cites·22 claims
- 0648US5568060ACircuit board insertion circuitry for high reliability backplanesTRANSWITCH CORP·Filed 1995·Granted Oct 22, 1996·11 cites·20 claims
- 0745US6205155B1Apparatus and method for limiting data bursts in ATM switch utilizing shared busTRANSWITCH CORP·Filed 1999·Granted Mar 20, 2001·19 cites·17 claims
- 0840US2002013893A1Real time debugger interface for embedded systemsTRANSWITCH CORP·Filed 2001·Application pending·0 cites
- 0940US2024297725A1Opportunistic Muting Of All-Digital Stations During Noisy AcquisitionIBIQUITY DIGITAL CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →