Inventor · disambiguated record
Eugene Saghi
Also filed as: SAGHI EUGENE
17 granted patents·1 pending application·109 citations·filing 2001–2014
92Inventor score
Top patents by PatentIndex Score
18 records- 0196US8943234B1Multi-protocol storage controllerLSI CORP·Filed 2013·Granted Jan 27, 2015·47 cites·19 claims
- 0290US9792245B2Peripheral component interconnect express (PCIe) devices with efficient memory mapping by remapping a plurality of base address registers (BARs)AVAGO TECHNOLOGIES GENERAL IP·Filed 2014·Granted Oct 17, 2017·19 cites·20 claims
- 0377US8077620B2Methods and apparatuses for processing packets in a credit-based flow control schemeSOLOMON RICHARD·Filed 2008·Granted Dec 13, 2011·10 cites·19 claims
- 0473US9424219B2Direct routing between address spaces through a nontransparent peripheral component interconnect express bridgeLSI CORP·Filed 2013·Granted Aug 23, 2016·3 cites·12 claims
- 0572US9424224B2PCIe tunneling through SASLSI CORP·Filed 2013·Granted Aug 23, 2016·3 cites·20 claims
- 0671US9009370B2Intelligent data buffering between interfacesLSI CORP·Filed 2013·Granted Apr 14, 2015·3 cites·12 claims
- 0771US8832499B2Methods and structure for trapping requests directed to hardware registers of an electronic circuitSAGHI EUGENE·Filed 2012·Granted Sep 9, 2014·3 cites·20 claims
- 0867US8745457B2Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signalsSAGHI EUGENE·Filed 2012·Granted Jun 3, 2014·2 cites·18 claims
- 0966US7913124B2Apparatus and methods for capture of flow control errors in clock domain crossing data transfersLSI CORP·Filed 2008·Granted Mar 22, 2011·4 cites·18 claims
- 1064US7646668B2Maintaining dynamic count of FIFO contents in multiple clock domainsLSI CORP·Filed 2008·Granted Jan 12, 2010·3 cites·10 claims
- 1162US6968409B1Method and apparatus of establishing a dynamically adjustable loop of delayed read commands for completion in a queue bufferLSI LOGIC CORP·Filed 2001·Granted Nov 22, 2005·9 cites·11 claims
- 1249US8176207B2System debug of input/output virtualization deviceSOLOMON RICHARD I·Filed 2008·Granted May 8, 2012·2 cites·10 claims
- 1349US7701977B2Method and apparatus to align and standardize packet based parallel interfacesLSI CORP·Filed 2008·Granted Apr 20, 2010·0 cites·20 claims
- 1447US7237043B2System for improving PCI write performanceLSI CORP·Filed 2003·Granted Jun 26, 2007·1 cites·11 claims
- 1547US2010011146A1Conveying Information With a PCI Express Tag FieldLSI CORP·Filed 2008·Application pending·0 cites
- 1641US8775888B2Methods and structure for correlating multiple test outputs of an integrated circuit acquired during separate instances of an eventSAGHI EUGENE·Filed 2012·Granted Jul 8, 2014·0 cites·20 claims
- 1741US8738979B2Methods and structure for correlation of test signals routed using different signaling pathwaysSMITH PAUL J·Filed 2012·Granted May 27, 2014·0 cites·20 claims
- 1840US8108574B2Apparatus and methods for translation of data formats between multiple interface typesUDELL JOHN C·Filed 2008·Granted Jan 31, 2012·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →