Inventor · disambiguated record
F. Erich Goetting
Also filed as: GOETTING F ERICH
57 granted patents·3,868 citations·filing 1990–2008
99Inventor score
Files withXILINX INC57
Top patents by PatentIndex Score
57 records- 0199US7499513B1Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuitXILINX INC·Filed 2005·Granted Mar 3, 2009·83 cites·25 claims
- 0299US5744979AFPGA having logic cells configured by SRAM memory cells and interconnect configured by antifusesXILINX INC·Filed 1996·Granted Apr 28, 1998·348 cites·3 claims
- 0399US5365125ALogic cell for field programmable gate array having optional internal feedback and optional cascadeXILINX INC·Filed 1992·Granted Nov 15, 1994·287 cites·9 claims
- 0498US7235999B2System monitor in a programmable logic deviceXILINX INC·Filed 2006·Granted Jun 26, 2007·59 cites·12 claims
- 0598US6191614B1FPGA configuration circuit including bus-based CRC registerXILINX INC·Filed 1999·Granted Feb 20, 2001·245 cites·2 claims
- 0697US7126372B2Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfigurationXILINX INC·Filed 2004·Granted Oct 24, 2006·151 cites·18 claims
- 0796US7230445B1System monitor in a programmable logic deviceXILINX INC·Filed 2006·Granted Jun 12, 2007·33 cites·20 claims
- 0896US7218137B2Reconfiguration port for dynamic reconfigurationXILINX INC·Filed 2004·Granted May 15, 2007·100 cites·31 claims
- 0996US7138820B2System monitor in a programmable logic deviceXILINX INC·Filed 2004·Granted Nov 21, 2006·73 cites·30 claims
- 1096US6429682B1Configuration bus interface circuit for FPGAsXILINX INC·Filed 2001·Granted Aug 6, 2002·83 cites·13 claims
- 1196US6204687B1Method and structure for configuring FPGASXILINX INC·Filed 1999·Granted Mar 20, 2001·336 cites·3 claims
- 1296US5386154ACompact logic cell for field programmable gate array chipXILINX INC·Filed 1992·Granted Jan 31, 1995·113 cites·8 claims
- 1395US7187742B1Synchronized multi-output digital clock managerXILINX INC·Filed 2000·Granted Mar 6, 2007·71 cites·17 claims
- 1495US6366117B1Nonvolatile/battery-backed key in PLDXILINX INC·Filed 2000·Granted Apr 2, 2002·126 cites·7 claims
- 1595US6262596B1Configuration bus interface circuit for FPGASXILINX INC·Filed 1999·Granted Jul 17, 2001·116 cites·19 claims
- 1694US6441641B1Programmable logic device with partial battery backupXILINX INC·Filed 2000·Granted Aug 27, 2002·113 cites·6 claims
- 1793US6289068B1Delay lock loop with clock phase shifterXILINX INC·Filed 1998·Granted Sep 11, 2001·169 cites·24 claims
- 1893US5958026AInput/output buffer supporting multiple I/O standardsXILINX INC·Filed 1997·Granted Sep 28, 1999·96 cites·16 claims
- 1993US5349248AAdaptive programming method for antifuse technologyXILINX INC·Filed 1992·Granted Sep 20, 1994·84 cites·16 claims
- 2092US7345507B1Multi-product die configurable as two or more programmable integrated circuits of different logic capacitiesXILINX INC·Filed 2006·Granted Mar 18, 2008·27 cites·20 claims
- 2192US5291079AConfiguration control unit for programming a field programmable gate array and reading array statusXILINX INC·Filed 1992·Granted Mar 1, 1994·70 cites·15 claims
- 2291US6525562B1Programmable logic device capable of preserving state data during partial or complete reconfigurationXILINX INC·Filed 2002·Granted Feb 25, 2003·38 cites·15 claims
- 2391US6294930B1FPGA with a plurality of input reference voltage levelsXILINX INC·Filed 2000·Granted Sep 25, 2001·31 cites·2 claims
- 2491US6204710B1Precision trim circuit for delay linesXILINX INC·Filed 1998·Granted Mar 20, 2001·85 cites·13 claims
- 2591US5367207AStructure and method for programming antifuses in an integrated circuit arrayXILINX INC·Filed 1990·Granted Nov 22, 1994·86 cites·18 claims
- 2690US8001511B1Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC diesXILINX INC·Filed 2008·Granted Aug 16, 2011·16 cites·9 claims
- 2790US7402443B1Methods of providing families of integrated circuits with similar dies partially disabled using product selection codesXILINX INC·Filed 2006·Granted Jul 22, 2008·20 cites·20 claims
- 2890US5498979AAdaptive programming method for antifuse technologyXILINX INC·Filed 1994·Granted Mar 12, 1996·52 cites·14 claims
- 2989US6507211B1Programmable logic device capable of preserving user data during partial or complete reconfigurationXILINX INC·Filed 1999·Granted Jan 14, 2003·52 cites·16 claims
- 3089US5877632AFPGA with a plurality of I/O voltage levelsXILINX INC·Filed 1997·Granted Mar 2, 1999·43 cites·7 claims
- 3188US5331226ALogic cell for field programmable gate array having optional input invertersXILINX INC·Filed 1992·Granted Jul 19, 1994·51 cites·5 claims
- 3287US7599299B2Dynamic reconfiguration of a system monitor (DRPORT)XILINX INC·Filed 2004·Granted Oct 6, 2009·35 cites·6 claims
- 3387US5500608ALogic cell for field programmable gate array having optional internal feedback and optional cascadeXILINX INC·Filed 1994·Granted Mar 19, 1996·41 cites·15 claims
- 3486US7010014B1Digital spread spectrum circuitryXILINX INC·Filed 2000·Granted Mar 7, 2006·39 cites·5 claims
- 3586US6049227AFPGA with a plurality of I/O voltage levelsXILINX INC·Filed 1998·Granted Apr 11, 2000·33 cites·15 claims
- 3684US7451421B1Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC diesXILINX INC·Filed 2006·Granted Nov 11, 2008·12 cites·8 claims
- 3784US7233532B2Reconfiguration port for dynamic reconfiguration-system monitor interfaceXILINX INC·Filed 2004·Granted Jun 19, 2007·26 cites·23 claims
- 3884US6775342B1Digital phase shifterXILINX INC·Filed 2000·Granted Aug 10, 2004·28 cites·31 claims
- 3983US5319254ALogic cell which can be configured as a latch without static one's problemXILINX INC·Filed 1992·Granted Jun 7, 1994·39 cites·3 claims
- 4082US7498192B1Methods of providing a family of related integrated circuits of different sizesXILINX INC·Filed 2006·Granted Mar 3, 2009·11 cites·20 claims
- 4180US7491576B1Yield-enhancing methods of providing a family of scaled integrated circuitsXILINX INC·Filed 2006·Granted Feb 17, 2009·10 cites·20 claims
- 4280US6587534B2Delay lock loop with clock phase shifterXILINX INC·Filed 2001·Granted Jul 1, 2003·21 cites·10 claims
- 4380US6191613B1Programmable logic device with delay-locked loopXILINX INC·Filed 1999·Granted Feb 20, 2001·37 cites·13 claims
- 4479US6448809B2FPGA with a plurality of input reference voltage levelsXILINX INC·Filed 2001·Granted Sep 10, 2002·14 cites·11 claims
- 4576US5912937ACMOS flip-flop having non-volatile storageXILINX INC·Filed 1997·Granted Jun 15, 1999·35 cites·10 claims
- 4675US7109750B2Reconfiguration port for dynamic reconfiguration-controllerXILINX INC·Filed 2004·Granted Sep 19, 2006·17 cites·35 claims
- 4773US6445232B1Digital clock multiplier and divider with output waveform shapingXILINX INC·Filed 2000·Granted Sep 3, 2002·19 cites·16 claims
- 4871US6086629AMethod for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffersXILINX INC·Filed 1997·Granted Jul 11, 2000·70 cites·16 claims
- 4957US5672966AHigh speed post-programming net packing methodXILINX INC·Filed 1995·Granted Sep 30, 1997·17 cites·10 claims
- 5055US5764534AMethod for providing placement information during design entryXILINX INC·Filed 1996·Granted Jun 9, 1998·30 cites·18 claims
Showing the top 50 of 57 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →