Inventor · disambiguated record
Farrukh Aquil
Also filed as: AQUIL FARRUKH
16 granted patents·9 pending applications·35 citations·filing 2006–2024
91Inventor score
Top patents by PatentIndex Score
25 records- 0197US11340686B2Optimizing power in a memory deviceRAMBUS INC·Filed 2020·Granted May 24, 2022·4 cites·20 claims
- 0296US11994930B2Optimizing power in a memory deviceRAMBUS INC·Filed 2022·Granted May 28, 2024·2 cites·20 claims
- 0388US11120863B2System and method for compensating for SDRAM signal timing drift through periodic write trainingQUALCOMM INC·Filed 2020·Granted Sep 14, 2021·3 cites·30 claims
- 0487US10761587B2Optimizing power in a memory deviceRAMBUS INC·Filed 2018·Granted Sep 1, 2020·4 cites·20 claims
- 0587US9734878B1Systems and methods for individually configuring dynamic random access memories sharing a common command access busQUALCOMM INC·Filed 2016·Granted Aug 15, 2017·5 cites·30 claims
- 0686US12346188B2Optimizing power in a memory deviceRAMBUS INC·Filed 2024·Granted Jul 1, 2025·0 cites·20 claims
- 0784US10133338B2Optimizing power in a memory deviceRAMBUS INC·Filed 2017·Granted Nov 20, 2018·2 cites·20 claims
- 0876US9645631B2Optimizing power in a memory deviceRAMBUS INC·Filed 2016·Granted May 9, 2017·2 cites·20 claims
- 0975US12468332B2Enhanced chip select signal trainingQUALCOMM INC·Filed 2023·Granted Nov 11, 2025·0 cites·30 claims
- 1075US7969807B2Memory that retains data when switching partial array self refresh settingsQIMONDA AG·Filed 2008·Granted Jun 28, 2011·10 cites·12 claims
- 1172US9431089B2Optimizing power in a memory deviceRAMBUS INC·Filed 2013·Granted Aug 30, 2016·2 cites·20 claims
- 1258US9734890B1Systems and methods for individually configuring dynamic random access memories sharing a common command access busQUALCOMM INC·Filed 2016·Granted Aug 15, 2017·1 cites·30 claims
- 1357US2025119059A1Dynamic circuit calibration during voltage change transitionsQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1455US11493949B2Clocking scheme to receive dataQUALCOMM INC·Filed 2020·Granted Nov 8, 2022·0 cites·20 claims
- 1555US2025077113A1Command bus training for memory systemQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1653US12444451B2Read data capture for a high-speed double data rate interfaceQUALCOMM INC·Filed 2024·Granted Oct 14, 2025·0 cites·20 claims
- 1751US2025259665A1Delay adjuster based clock qualifier timing enhancement for memory interfaceQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1850US12100474B2Clock qualifier enhancement for external double data rate memory interfacesQUALCOMM INC·Filed 2022·Granted Sep 24, 2024·0 cites·30 claims
- 1946US10642337B2Active power management in a computing device subsystem based on micro-idle durationQUALCOMM INC·Filed 2017·Granted May 5, 2020·0 cites·30 claims
- 2036US2007252638A1Method and apparatus for temperature compensating off chip driver (OCD) circuitAQUIL FARRUKH·Filed 2006·Application pending·0 cites
- 2134US2008137470A1Memory with data clock receiver and command/address clock receiverSCHNELL JOSEF·Filed 2006·Application pending·0 cites
- 2234US2007291572A1Clock circuit for semiconductor memorySCHNELL JOSEF·Filed 2006·Application pending·0 cites
- 2334US2008228950A1Memory power down mode exit method and systemQIMONDA NORTH AMERICA CORP·Filed 2007·Application pending·0 cites
- 2434US2008137471A1Memory with clock distribution optionsSCHNELL JOSEF·Filed 2006·Application pending·0 cites
- 2534US2008137472A1Memory including first and second receiversSCHNELL JOSEF·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →