Inventor · disambiguated record
Faraydon Pakbaz
Also filed as: PAKBAZ FARAYDON
10 granted patents·2 pending applications·59 citations·filing 2001–2016
87Inventor score
Top patents by PatentIndex Score
12 records- 0189US8612815B2Asynchronous circuit with an at-speed built-in self-test (BIST) architecturePAKBAZ FARAYDON·Filed 2011·Granted Dec 17, 2013·13 cites·25 claims
- 0281US8188765B2Circuit and method for asynchronous pipeline processing with variable request signal delayOUELLETTE MICHAEL R·Filed 2010·Granted May 29, 2012·7 cites·20 claims
- 0380US8988140B2Real-time adaptive voltage control of logic blocksIBM·Filed 2013·Granted Mar 24, 2015·5 cites·19 claims
- 0479US10651135B2Tamper detection for a chip packageMARVELL INT LTD·Filed 2016·Granted May 12, 2020·2 cites·19 claims
- 0577US7533357B2Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysisIBM·Filed 2006·Granted May 12, 2009·10 cites·16 claims
- 0672US8756549B2Integrated circuit chip incorporating embedded thermal radiators for localized, on-demand, heating and a system and method for designing such an integrated circuit chipGRAF RICHARD S·Filed 2011·Granted Jun 17, 2014·6 cites·14 claims
- 0767US6662352B2Method of assigning chip I/O's to package channelsIBM·Filed 2001·Granted Dec 9, 2003·13 cites·20 claims
- 0861US7603639B2Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitryIBM·Filed 2007·Granted Oct 13, 2009·2 cites·20 claims
- 0950US8648634B2Input jitter filter for a phase-locked loop (PLL)KELKAR RAM·Filed 2012·Granted Feb 11, 2014·1 cites·18 claims
- 1046US7084615B1Performance measurement of device dedicated to phase locked loop using second order system approximationIBM·Filed 2005·Granted Aug 1, 2006·0 cites·20 claims
- 1141US2009112558A1Method for simultaneous circuit board and integrated circuit switching noise analysis and mitigationGAROFANO UMBERTO·Filed 2007·Application pending·0 cites
- 1240US2006190229A1Method of modeling a portion of an electrical circuit using a pole-zero approximation of an s-parameter transfer function of the circuit portionIBM·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →