Inventor · disambiguated record
Fangyun Richter
Also filed as: RICHTER FANGYUN
15 granted patents·106 citations·filing 2002–2017
91Inventor score
Top patents by PatentIndex Score
15 records- 0188US8664725B1Strain enhanced transistors with adjustable layoutsVENKITACHALAM GIRISH·Filed 2011·Granted Mar 4, 2014·12 cites·18 claims
- 0288US8159044B1Density transition zones for integrated circuitsCHEN SHUXIAN·Filed 2009·Granted Apr 17, 2012·18 cites·20 claims
- 0388US6972466B1Bipolar transistors with low base resistance for CMOS integrated circuitsALTERA CORP·Filed 2004·Granted Dec 6, 2005·42 cites·8 claims
- 0486US10541205B1Manufacture of interconnects for integration of multiple integrated circuitsINTEL CORP·Filed 2017·Granted Jan 21, 2020·5 cites·18 claims
- 0583US8835265B1High-k dielectric device and processHSU CHE TA·Filed 2012·Granted Sep 16, 2014·6 cites·12 claims
- 0677US7285454B1Bipolar transistors with low base resistance for CMOS integrated circuitsALTERA CORP·Filed 2005·Granted Oct 23, 2007·6 cites·18 claims
- 0774US9634094B1Strain-enhanced transistors with adjustable layoutsALTERA CORP·Filed 2014·Granted Apr 25, 2017·2 cites·7 claims
- 0872US9166045B1High-k dielectric device and processALTERA CORP·Filed 2014·Granted Oct 20, 2015·2 cites·16 claims
- 0967US6773987B1Method and apparatus for reducing charge loss in a nonvolatile memory cellALTERA CORP·Filed 2002·Granted Aug 10, 2004·11 cites·10 claims
- 1064US9099531B1Metal routing in advanced process technologiesALTERA CORP·Filed 2014·Granted Aug 4, 2015·1 cites·20 claims
- 1162US9484411B1Integrated circuit and a method to optimize strain inducing compositesALTERA CORP·Filed 2014·Granted Nov 1, 2016·1 cites·11 claims
- 1246US8765541B1Integrated circuit and a method to optimize strain inducing compositesVENKITACHALAM GIRISH·Filed 2011·Granted Jul 1, 2014·0 cites·17 claims
- 1340US7291546B1Method and apparatus for reducing charge loss in a nonvolatile memory cellALTERA CORP·Filed 2004·Granted Nov 6, 2007·0 cites·25 claims
- 1436US8921217B2Methods of forming gate structures for reduced leakageLIN WUU-CHERNG·Filed 2011·Granted Dec 30, 2014·0 cites·20 claims
- 1536US8912104B1Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimizationRATAKONDA DEEPA·Filed 2011·Granted Dec 16, 2014·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →