Inventor · disambiguated record
Fangxing Wei
Also filed as: WEI FANGXING
24 granted patents·165 citations·filing 1998–2019
95Inventor score
Top patents by PatentIndex Score
24 records- 0196US9805773B1Dual-range clock duty cycle correctorINTEL CORP·Filed 2016·Granted Oct 31, 2017·26 cites·22 claims
- 0294US10164618B1Jitter cancellation with automatic performance adjustmentMICRON TECHNOLOGY INC·Filed 2017·Granted Dec 25, 2018·11 cites·25 claims
- 0391US10270453B2Coarse delay lock estimation for digital DLL circuitsINTEL CORP·Filed 2016·Granted Apr 23, 2019·10 cites·19 claims
- 0489US9407273B1Digital delay-locked loop (DLL) trainingINTEL CORP·Filed 2015·Granted Aug 2, 2016·8 cites·25 claims
- 0586US10476488B2Jitter cancellation with automatic performance adjustmentMICRON TECHNOLOGY INC·Filed 2018·Granted Nov 12, 2019·3 cites·20 claims
- 0685US9614533B2Digital phase control with programmable tracking slopeINTEL CORP·Filed 2015·Granted Apr 4, 2017·6 cites·23 claims
- 0784US9231519B2Temperature compensation for oscillatorWEI FANGXING·Filed 2012·Granted Jan 5, 2016·7 cites·15 claims
- 0880US9455726B1XOR (exclusive or) based triangular mixing for digital phase controlINTEL CORP·Filed 2015·Granted Sep 27, 2016·5 cites·20 claims
- 0972US6445329B1High speed analog to digital converterATI INT SRL·Filed 2000·Granted Sep 3, 2002·25 cites·24 claims
- 1071US6831492B1Common-bias and differential structure based DLLATI INT SRL·Filed 2000·Granted Dec 14, 2004·19 cites·7 claims
- 1164US11018676B2Coarse delay lock estimation for digital DLL circuitsINTEL CORP·Filed 2019·Granted May 25, 2021·1 cites·7 claims
- 1259US10574241B2Digital phase control with programmable tracking slope having a programmable linear decoder using a coarse code and a fine code to generate delay adjustments to the phase of an input signalINTEL CORP·Filed 2017·Granted Feb 25, 2020·1 cites·24 claims
- 1354US10797685B2Jitter cancellation with automatic performance adjustmentMICRON TECHNOLOGY INC·Filed 2019·Granted Oct 6, 2020·0 cites·20 claims
- 1452US9112671B2Gated ring oscillator-based digital eye width monitor for high-speed I/O eye width measurementWEI FANGXING·Filed 2012·Granted Aug 18, 2015·1 cites·25 claims
- 1550US6614675B1Pipelined content addressable memory with read only element encoding schemeATI INT SRL·Filed 2000·Granted Sep 2, 2003·7 cites·16 claims
- 1649US6137735AColumn redundancy circuit with reduced signal path delayMOSAID TECHNOLOGIES INC·Filed 1998·Granted Oct 24, 2000·13 cites·7 claims
- 1748US10122526B2Phase detector in a delay locked loopINTEL CORP·Filed 2017·Granted Nov 6, 2018·0 cites·23 claims
- 1848US8929499B2System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolatorINTEL CORP·Filed 2012·Granted Jan 6, 2015·0 cites·24 claims
- 1947US9166773B2System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolatorINTEL CORP·Filed 2015·Granted Oct 20, 2015·0 cites·20 claims
- 2047US8059756B2High-speed serial link receiver with centrally controlled offset cancellation and methodWEI FANGXING·Filed 2008·Granted Nov 15, 2011·0 cites·20 claims
- 2147US7391824B2High-speed serial link receiver with centrally controlled offset cancellation and methodINTEL CORP·Filed 2003·Granted Jun 24, 2008·1 cites·3 claims
- 2244US7249273B2Synchronized serial interfaceINTEL CORP·Filed 2003·Granted Jul 24, 2007·1 cites·27 claims
- 2344US6301318B1Pipelined phase detector for clock recoveryPMC SIERRA LTD·Filed 1998·Granted Oct 9, 2001·20 cites·13 claims
- 2438US9548747B2Glitch-free digitally controlled oscillator code updateINTEL CORP·Filed 2015·Granted Jan 17, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →