Inventor · disambiguated record
Farid A. Yazdy
Also filed as: YAZDY FARID · YAZDY FARID A
15 granted patents·377 citations·filing 1987–2002
94Inventor score
Top patents by PatentIndex Score
15 records- 0190US4887240AStaggered refresh for dram arrayNAT SEMICONDUCTOR CORP·Filed 1987·Granted Dec 12, 1989·91 cites·7 claims
- 0265US5237573AMethod and apparatus for selectively switching between input signalsAPPLE COMPUTER·Filed 1992·Granted Aug 17, 1993·18 cites·10 claims
- 0363US5845327ACache coherency where multiple processors may access the same data over independent access pathsAPPLE COMPUTER·Filed 1997·Granted Dec 1, 1998·48 cites·7 claims
- 0463US5500827AMethod and apparatus for improved DRAM refresh operationAPPLE COMPUTER·Filed 1995·Granted Mar 19, 1996·23 cites·22 claims
- 0562US5515514APeripheral processor card for upgrading a computerAPPLE COMPUTER·Filed 1995·Granted May 7, 1996·42 cites·26 claims
- 0661US5546547AMemory bus arbiter for a computer system having a dsp co-processorAPPLE COMPUTER·Filed 1994·Granted Aug 13, 1996·38 cites·8 claims
- 0757US5901295AAddress and data bus arbiter for pipelined transactions on a split busAPPLE COMPUTER·Filed 1995·Granted May 4, 1999·34 cites·20 claims
- 0853US7286527B2Method and apparatus for round trip delay measurement in a bi-directional, point-to-point, serial data channelBROCADE COMM SYSTEMS INC·Filed 2002·Granted Oct 23, 2007·2 cites·37 claims
- 0946US6373493B1Hardware graphics accelerator having access to multiple types of memory including cached memoryAPPLE COMPUTER·Filed 1995·Granted Apr 16, 2002·15 cites·14 claims
- 1043US6256710B1Cache management during cache inhibited transactions for increasing cache efficiencyAPPLE COMPUTER·Filed 1995·Granted Jul 3, 2001·15 cites·10 claims
- 1143US5600802AMethods and apparatus for translating incompatible bus transactionsAPPLE COMPUTER·Filed 1994·Granted Feb 4, 1997·14 cites·2 claims
- 1240US5603007AMethods and apparatus for controlling back-to-back burst reads in a cache systemAPPLE COMPUTER·Filed 1994·Granted Feb 11, 1997·12 cites·5 claims
- 1338US5812815AAddress tenure control for cache management wherein bus master addresses are internally latched in a cache controllerAPPLE COMPUTER·Filed 1995·Granted Sep 22, 1998·11 cites·11 claims
- 1436US5708783AData bus arbiter for pipelined transactions on a split busAPPLE COMPUTER·Filed 1995·Granted Jan 13, 1998·9 cites·9 claims
- 1532US5815676AAddress bus arbiter for pipelined transactions on a split busAPPLE COMPUTER·Filed 1997·Granted Sep 29, 1998·5 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →