Inventor · disambiguated record
Francisco A. Cano
Also filed as: CANO FRANCISCO · CANO FRANCISCO A · CANO FRANCISCO ADOLFO
21 granted patents·6 pending applications·495 citations·filing 1996–2024
95Inventor score
Top patents by PatentIndex Score
27 records- 0187US6581201B2Method for power routing and distribution in an integrated circuit with multiple interconnect layersTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 17, 2003·44 cites·11 claims
- 0285US11568951B2Screening of memory circuitsTEXAS INSTRUMENTS INC·Filed 2020·Granted Jan 31, 2023·2 cites·17 claims
- 0385US7446553B2Semiconductor device testingTEXAS INSTRUMENTS INC·Filed 2007·Granted Nov 4, 2008·9 cites·7 claims
- 0484US6308307B1Method for power routing and distribution in an integrated circuit with multiple interconnect layersTEXAS INSTRUMENTS INC·Filed 1999·Granted Oct 23, 2001·70 cites·22 claims
- 0583US6038383AMethod and apparatus for determining signal line interconnect widths to ensure electromigration reliabilityTEXAS INSTRUMENTS INC·Filed 1997·Granted Mar 14, 2000·137 cites·22 claims
- 0682US11831309B2Stress reduction on stacked transistor circuitsTEXAS INSTRUMENTS INC·Filed 2019·Granted Nov 28, 2023·3 cites·19 claims
- 0781US11626875B2Stress reduction on stacked transistor circuitsTEXAS INSTRUMENTS INC·Filed 2019·Granted Apr 11, 2023·3 cites·6 claims
- 0877US7365556B2Semiconductor device testingTEXAS INSTRUMENTS INC·Filed 2005·Granted Apr 29, 2008·6 cites·4 claims
- 0974US6363516B1Method for hierarchical parasitic extraction of a CMOS designTEXAS INSTRUMENTS INC·Filed 1999·Granted Mar 26, 2002·84 cites·9 claims
- 1073US12476636B2Stress reduction on stacked transistor circuitsTEXAS INSTRUMENTS INC·Filed 2023·Granted Nov 18, 2025·0 cites·20 claims
- 1173US5745421AMethod and apparatus for self-timed precharge of bit lines in a memoryTEXAS INSTRUMENTS INC·Filed 1996·Granted Apr 28, 1998·35 cites·26 claims
- 1271US12212317B2Stress reduction on stacked transistor circuitsTEXAS INSTRUMENTS INC·Filed 2023·Granted Jan 28, 2025·0 cites·20 claims
- 1370US7382147B2Semiconductor device testingTEXAS INSTRUMENTS INC·Filed 2007·Granted Jun 3, 2008·4 cites·8 claims
- 1468US6253359B1Method for analyzing circuit delays caused by capacitive coupling in digital circuitsTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 26, 2001·53 cites·19 claims
- 1567US11881275B2Screening of memory circuitsTEXAS INSTRUMENTS INC·Filed 2022·Granted Jan 23, 2024·0 cites·16 claims
- 1662US6381704B1Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessorTEXAS INSTRUMENTS INC·Filed 1999·Granted Apr 30, 2002·28 cites·19 claims
- 1761US7446552B2Semiconductor device testingTEXAS INSTRUMENTS INC·Filed 2007·Granted Nov 4, 2008·2 cites·11 claims
- 1859US8890588B2Circuits and methods for asymmetric aging preventionTEXAS INSTRUMENTS INC·Filed 2013·Granted Nov 18, 2014·2 cites·18 claims
- 1957US2025370042A1Clock signal control for scan-chain testingTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 2054US2014159800A1Simplified Adaptive Voltage Scaling Using Lookup-Table and Analog Temperature Sensor to Improve Performance Prediction Across TemperatureTEXAS INSTRUMENTS INC·Filed 2013·Application pending·0 cites
- 2153US12301229B2Adaptive voltage scaling using temperature and performance sensorsTEXAS INSTRUMENTS INC·Filed 2019·Granted May 13, 2025·0 cites·15 claims
- 2250US2024037180A1Transient current managementTEXAS INSTRUMENTS INC·Filed 2022·Application pending·0 cites
- 2348US5835421AMethod and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memoryTEXAS INSTRUMENTS INC·Filed 1996·Granted Nov 10, 1998·12 cites·23 claims
- 2446US8144533B2Compensatory memory systemCANO FRANCISCO A·Filed 2010·Granted Mar 27, 2012·1 cites·15 claims
- 2546US2014159801A1Performance Adaptive Voltage Scaling with Performance Tracking SensorTEXAS INSTRUMENTS INC·Filed 2013·Application pending·0 cites
- 2640US2012266123A1Coherent analysis of asymmetric aging and statistical process variation in electronic circuitsJAIN PALKESH·Filed 2011·Application pending·0 cites
- 2736US2013002297A1Bias temperature instability-resistant circuitsTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →