Inventor · disambiguated record
Friedrich Hapke
Also filed as: HAPKE FRIEDRICH
18 granted patents·4 pending applications·219 citations·filing 1980–2015
94Inventor score
Top patents by PatentIndex Score
22 records- 0188US4336495AIntegrated circuit arrangement in MOS-technology with field-effect transistorsPHILIPS CORP·Filed 1980·Granted Jun 22, 1982·50 cites·2 claims
- 0287US4339710AMOS Integrated test circuit using field effect transistorsPHILIPS CORP·Filed 1980·Granted Jul 13, 1982·50 cites·1 claims
- 0382US4398146ATest circuit for MOS devicesPHILIPS CORP·Filed 1980·Granted Aug 9, 1983·45 cites·3 claims
- 0471US8103925B2On-chip logic to support compressed X-masking for BISTHAPKE FRIEDRICH·Filed 2009·Granted Jan 24, 2012·6 cites·8 claims
- 0571US7376873B2Method and system for selectively masking test responsesNXP BV·Filed 2004·Granted May 20, 2008·16 cites·9 claims
- 0670US8250420B2Testable integrated circuit and test data generation methodHAPKE FRIEDRICH·Filed 2008·Granted Aug 21, 2012·7 cites·17 claims
- 0769US6789221B2Integrated circuit with self-test circuitKONINKL PHILIPS ELECTRONICS NV·Filed 2001·Granted Sep 7, 2004·14 cites·5 claims
- 0867US8112686B2Deterministic logic built-in self-test stimuli generationHAPKE FRIEDRICH·Filed 2009·Granted Feb 7, 2012·5 cites·16 claims
- 0963US8689069B2Multi-targeting boolean satisfiability-based test pattern generationKRENZ-BAATH RENE·Filed 2011·Granted Apr 1, 2014·3 cites·14 claims
- 1060US8990760B2Cell-aware fault model generation for delay faultsHAPKE FRIEDRICH·Filed 2011·Granted Mar 24, 2015·2 cites·26 claims
- 1157US8423845B2On-chip logic to log failures during production testing and enable debugging for failure diagnosisHAPKE FRIEDRICH·Filed 2009·Granted Apr 16, 2013·3 cites·12 claims
- 1255US8448008B2High speed clock controlHAPKE FRIEDRICH·Filed 2010·Granted May 21, 2013·1 cites·8 claims
- 1351US6789219B2Arrangement and method of testing an integrated circuitKONINKL PHILIPS ELECTRONICS NV·Filed 2001·Granted Sep 7, 2004·7 cites·4 claims
- 1449US7039844B2Integrated circuit with self-testing circuitKONINKL PHILIPS ELECTRONICS NV·Filed 2003·Granted May 2, 2006·4 cites·13 claims
- 1547US2010253381A1On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIST DesignsHAPKE FRIEDRICH·Filed 2009·Application pending·0 cites
- 1643US7143322B2Arrangement and method of testing an integrated circuitKONINKL PHILIPS ELECTRONICS NV·Filed 2001·Granted Nov 28, 2006·2 cites·3 claims
- 1743US7139953B2Integrated circuit with test circuitKONINKL PHILIPS ELECTRONICS NV·Filed 2003·Granted Nov 21, 2006·2 cites·5 claims
- 1843US6768292B2Arrangement and method having a data word generator for testing integrated circuitsKONINKL PHILIPS ELECTRONICS NV·Filed 2002·Granted Jul 27, 2004·2 cites·10 claims
- 1936US7870453B2Circuit arrangement and method of testing an application circuit provided in said circuit arrangementNXP BV·Filed 2005·Granted Jan 11, 2011·0 cites·7 claims
- 2036US2015234978A1Cell Internal Defect DiagnosisMENTOR GRAPHICS CORP·Filed 2015·Application pending·0 cites
- 2135US2009013230A1Circuit arrangement and method of testing and/or diagnosing the sameNXP BV·Filed 2005·Application pending·0 cites
- 2233US2010229061A1Cell-Aware Fault Model Creation And Pattern GenerationHAPKE FRIEDRICH·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →