Inventor · disambiguated record
Fu-Chin Tsai
Also filed as: TSAI FU-CHIN
15 granted patents·1 pending application·46 citations·filing 2016–2023
89Inventor score
Files withREALTEK SEMICONDUCTOR CORP16
Top patents by PatentIndex Score
16 records- 0197US10998061B1Memory system and memory access interface device thereofREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted May 4, 2021·9 cites·16 claims
- 0292US10522204B1Memory signal phase difference calibration circuit and methodREALTEK SEMICONDUCTOR CORP·Filed 2018·Granted Dec 31, 2019·14 cites·20 claims
- 0387US10978118B1DDR SDRAM signal calibration device and methodREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Apr 13, 2021·7 cites·20 claims
- 0486US10741231B1Memory access interface device including phase and duty cycle adjusting circuits for memory access signalsREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Aug 11, 2020·4 cites·11 claims
- 0582US9570130B2Memory system and memory physical layer interface circuitREALTEK SEMICONDUCTOR CORP·Filed 2016·Granted Feb 14, 2017·6 cites·20 claims
- 0677US10916278B1Memory controller and memory data receiving method for generate better sampling clock signalREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Feb 9, 2021·4 cites·17 claims
- 0775US10998020B1Memory system and memory access interface device thereofREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted May 4, 2021·1 cites·18 claims
- 0864US11315656B1Detection circuit and detection methodREALTEK SEMICONDUCTOR CORP·Filed 2021·Granted Apr 26, 2022·0 cites·16 claims
- 0961US11270745B2Method of foreground auto-calibrating data reception window and related deviceREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Mar 8, 2022·1 cites·12 claims
- 1057US12417795B2Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory deviceREALTEK SEMICONDUCTOR CORP·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
- 1155US12300330B2Memory system and memory access interface device thereof for supporting different speed modesREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted May 13, 2025·0 cites·20 claims
- 1251US12429902B2Memory system, memory access interface device and operation method thereofREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Sep 30, 2025·0 cites·18 claims
- 1349US12020773B2Memory system and memory access interface device thereof including single data rate (SDR) and double data rate (DDR) modesREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Jun 25, 2024·0 cites·10 claims
- 1449US11823770B1Memory system and memory access interface device thereofREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Nov 21, 2023·0 cites·20 claims
- 1548US12009056B2Data transmission apparatus and method having clock gating mechanismREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Jun 11, 2024·0 cites·16 claims
- 1647US2024310869A1Memory system, memory access interface device and operation method thereofREALTEK SEMICONDUCTOR CORP·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →