Inventor · disambiguated record
Gabor Bobok
Also filed as: BOBOK GABOR
15 granted patents·4 pending applications·35 citations·filing 2005–2023
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
19 records- 0176US8255848B2Logic design verification techniques for liveness checking with retimingBAUMGARTNER JASON R·Filed 2009·Granted Aug 28, 2012·7 cites·13 claims
- 0271US8230406B2Compiler option consistency checking during incremental hardware design language compilationCARBONE RICHARD L H·Filed 2006·Granted Jul 24, 2012·10 cites·16 claims
- 0370US9286426B2Method and apparatus for testingIBM·Filed 2014·Granted Mar 15, 2016·3 cites·18 claims
- 0466US7493248B2Method, system and program product supporting phase events in a simulation model of a digital systemIBM·Filed 2006·Granted Feb 17, 2009·3 cites·3 claims
- 0564US7912694B2Print events in the simulation of a digital systemIBM·Filed 2007·Granted Mar 22, 2011·3 cites·6 claims
- 0664US7617085B2Program product supporting specification of signals for simulation result viewingIBM·Filed 2008·Granted Nov 10, 2009·2 cites·15 claims
- 0762US8407641B2Logic design verification techniques for liveness checking with retimingBAUMGARTNER JASON R·Filed 2012·Granted Mar 26, 2013·1 cites·13 claims
- 0861US7823097B2Unrolling hardware design generate statements in a source window debuggerIBM·Filed 2006·Granted Oct 26, 2010·2 cites·18 claims
- 0959US7711537B2Signals for simulation result viewingIBM·Filed 2006·Granted May 4, 2010·1 cites·23 claims
- 1057US7552043B2Method, system and program product for selectively removing instrumentation logic from a simulation modelIBM·Filed 2005·Granted Jun 23, 2009·1 cites·1 claims
- 1156US8108199B2Phase events in a simulation model of a digital systemBOBOK GABOR·Filed 2008·Granted Jan 31, 2012·1 cites·19 claims
- 1255US8160857B2Selective compilation of a simulation model in view of unavailable higher level signalsBOBOK GABOR·Filed 2008·Granted Apr 17, 2012·1 cites·15 claims
- 1355US2025124202A1Verifying multi-cycle interconnect synthesis optimization in automatically generated physical hierarchy chip designIBM·Filed 2023·Application pending·0 cites
- 1453US8713494B2Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessingIBM·Filed 2013·Granted Apr 29, 2014·0 cites·9 claims
- 1547US2008195368A1Method, system and program product for selectively removing instrumentation logic from a simulation modelBOBOK GABOR·Filed 2008·Application pending·0 cites
- 1647US2023072735A1Refinement of an integrated circuit designIBM·Filed 2021·Application pending·0 cites
- 1745US8495533B2Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessingDRASNY GABOR·Filed 2006·Granted Jul 23, 2013·0 cites·17 claims
- 1845US2024152676A1Early power estimation on a derived physical hierarchy in chip designIBM·Filed 2022·Application pending·0 cites
- 1942US7506287B2Method, system, and program product for pre-compile processing of hardware design language (HDL) source filesIBM·Filed 2006·Granted Mar 17, 2009·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →